MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/02/2023
Public

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Document Table of Contents

5.1.5. Port and Secure Channel Mapping

Table 30.  Mapping between MACsec Ports and SCs/SAs
Port (Identify through AXI-ST TID[5:0]) TX SC RX SC SA
Port 0 (TID = 0) TX_LANE_SC0_*[0], TX_LANE_SC1_*[0] CSRs RX_LANE_SC0_*[0], RX_LANE_SC1_*[0] CSRs TX_LANE_SC0_SA*[0], TX_LANE_SC1_SA*[0], RX_LANE_SC0_SA*[0], RX_LANE_SC1_SA*[0] CSRs
Port 1 (TID = 1) TX_LANE_SC0_*[1], TX_LANE_SC1_*[1] CSRs RX_LANE_SC0_*[1], RX_LANE_SC1_*[1] CSRs TX_LANE_SC0_SA*[1], TX_LANE_SC1_SA*[1], RX_LANE_SC0_SA*[1], RX_LANE_SC1_SA*[1] CSRs
: : : :
Port 63 (TID = 63) TX_LANE_SC0_*[63], TX_LANE_SC1_*[63] CSRs RX_LANE_SC0_*[63], RX_LANE_SC1_*[63] CSRs TX_LANE_SC0_SA*[63], TX_LANE_SC1_SA*[63], RX_LANE_SC0_SA*[63], RX_LANE_SC1_SA*[63] CSRs

The MACsec IP supports a maximum of 64 ports on the user interface. Traffic on each port is identified through the AXI-ST TID field. 2 Tx SCs and 2 Rx SCs are assigned to each port and each SC consists of 4 SAs. Each time only 1 Tx SA can be active while there can be multiple Rx SAs active together.

The above table shows the mapping between the MACsec IP ports and SCs/SAs. SCs and SAs are kept in the CSR and the contents are programmed by the SW.

The MACsec IP supports a maximum of 64 Controlled Ports and 1024 Crypto channels. Each port is assigned with 16 Crypto channels based on this setting. If you would like to have more than 16 Crypto channels assigned to a single port, the maximum number of supported Controlled ports can be reduced. For example, if MAX_CRYPTO_CH = 1024 and MAX_CTRL_PORT = 32, 32 Crypto channels are assigned to each port/stream. The Crypto secure channels assigned to each port/stream follow the table below. Note that the Tx port is always fixed to 2 SCs regardless of the number of Tx ports configured in the system.
Table 31.  Crypto Secure Channel Assignments for Each Port/Stream
Port (Identify through AXI-ST TID[5:0]) TX SC RX SC
Port 0 (TID = 0)

TX_LANE_SC0_*[0],

TX_LANE_SC1_*[0] CSRs

for each $port (0 .. (MAX_CRYPTO_CH/16 - 1) )

RX_LANE_SC0_*[$port MOD

(MAX_CTRL_PORT - MAX_TX_TID) == 0],

RX_LANE_SC1_*[$port MOD (MAX_CTRL_PORT - MAX_TX_TID) == 0] CSRs

Port 1 (TID = 1)

TX_LANE_SC0_*[1],

TX_LANE_SC1_*[1] CSRs

for each $port (0 .. (MAX_CRYPTO_CH/16 - 1) )

RX_LANE_SC0_*[$port MOD (MAX_CTRL_PORT - MAX_TX_TID) == 1],

RX_LANE_SC1_*[$port MOD (MAX_CTRL_PORT - MAX_TX_TID) == 1] CSRs

: : :
TX Port MAX_TX_TID - 1 (TID = MAX_TX_TID - 1)

TX_LANE_SC0_*[MAX_TX_TID-1],

TX_LANE_SC1_*[MAX_TX_TID-1] CSRs

for each $port (0 .. (MAX_CRYPTO_CH/16 - 1) )

RX_LANE_SC0_*[$port MOD (MAX_CTRL_PORT - MAX_TX_TID) == (MAX_CTRL_PORT - MAX_TX_TID) - 1],

RX_LANE_SC1_*[$port MOD (MAX_CTRL_PORT - MAX_TX_TID) == (MAX_CTRL_PORT - MAX_TX_TID) - 1] CSRs