MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1. MACsec Intel FPGA IP Parameter Settings

Table 23.  MACsec IP Parameter Settings
Parameter Supported Values Default Settings Parameter Description
Topology Tab
Snapshot Enable Enable, Disable Disable Snapshot Enable for Statistics Counters.
Control Port
  • ENCRYPT_DECRYPT
  • ENCRYPT_ONLY
  • DECRYPT_ONLY
ENCRYPT_DECRYPT

Controlled ports for encryption and decryption lanes.

Uncontrolled Port Enable Enable, Disable Enable Indicates whether the uncontrolled ports for both transmit and receive lanes are enabled to receive user traffic. When disabled, the uncontrolled ports are hidden from the user.
Number of TX+RX Ports 1-64 4 The number of Controlled Ports supported in MACsec for all ports and streams. In ENCRYPT_DECRYPT mode, the number of TX ports always equals the number of RX ports.
Interface Property Tab
Port VLAN Clear Enable, Disable Enable Defines whether VLLAN Clear is supported for Port X.
User Data Width
  • 256
  • 512
512 Width of data bus inside the MACsec IP's Port MUX & DEMUX blocks. This indicates the width of data after being muxed which is coming into the MACsec IP and the width of data before demuxing and being sent out of the MACsec IP. Supported values are 256 and 512.
Metadata Enable Enable, Disable Disable Indicates there is user metadata which is tagged along with incoming/outgoing packets into the MACsec IP. Required to support PTP use case.
Port-Specific Settings
Select Port 0-64 0 Selects the port for which parameters are to be configured.
Port Data Width
  • 64
  • 128
  • 256
  • 512
64 Width of the AXI-ST data ports at the edge of the MACsec IP as presented to the MUX and DEMUX blocks. This indicates the width of AXI-ST data ports before being muxed which is coming into the MACsec IP and the width of data after demuxing and being sent out of the MACsec IP. Supported values are 64, 128, 256, and 512.
Arbiter Ready Latency 0-16 0 Mux/Demux per-port ready latency on the AXI-ST ports at the edge of the MACsec IP. Defines the association between assertion of the READY signal and the corresponding VALID on the Port Mux/Demux and MACsec SIP interface.
802_1AE-2018 Options Tab
Validate Frames Strict, Check, Disable, Null Strict Indicates the transmitted/received frames check level.
Protect Frames Enable, Disable Enable Frames Protection Enable
Replay Protect Enable, Disable Enable Enables Anti-Replay Protection check on packets which go through the RX path.
XPN Mode Enable, Disable Enable Indicates whether the 64b Extended Packet Number is supported.
Example Designs Tab
Example Design Files
Example Design:
  • 1x25G
  • 4x25G
  • 1x100G
1x25G Selects the supported example design to be generated.

Acknowledgement:

The example design generates with only the Example Design Options specified in the drop-down menu. No other IP parameters that you specify applies to the example design generation.

Checked, Unchecked Unchecked Required to be checked to generate an example design. When checked, you acknowledge that the example design generates with ONLY the Example Design options specified in the drop-down menu, and that no other IP parameters which you specify apply to the generated Example Design.
Generated HDL Format
General file format Verilog Verilog HDL format of generated files.