MACsec Intel® FPGA IP User Guide

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ID 736108
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Functional Description 6. Configuration Registers for MACsec IP 7. MACsec Intel® FPGA IP Example Design 8. MACsec Intel FPGA IP User Guide Archives 9. Document Revision History for the MACsec Intel FPGA IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Device Speed Grade Support and Theoretical Throughput 1.6. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Description 1.2.2. IP Core Applications
1.2.2. IP Core Applications x
1.2.2.1. SmartNIC 1.2.2.2. Ethernet Bridge + Inline MACsec
2. Interface Overview x
2.1. Block Diagram 2.2. Interfaces 2.3. Clocking Domains
2.2. Interfaces x
2.2.1. IP Interface Signals 2.2.2. IP Interface Signal Timing Diagram/Waveforms 2.2.3. Clocks, Resets, and Interrupts
2.2.1. IP Interface Signals x
2.2.1.1. Common Port Mux Interface 2.2.1.2. Common Port Demux Interface 2.2.1.3. Controlled Port Mux Interface 2.2.1.4. Controlled Port Demux Interface 2.2.1.5. Uncontrolled Port RX Interface 2.2.1.6. Uncontrolled Port TX Interface 2.2.1.7. Management Interface 2.2.1.8. Decrypt Port Mux Management Interface 2.2.1.9. Decrypt Port Demux Management Interface 2.2.1.10. Encrypt Port Mux Management Interface 2.2.1.11. Encrypt Port Demux Management Interface 2.2.1.12. Crypto IP Management Bus 2.2.1.13. Miscellaneous Control Signals
2.2.2. IP Interface Signal Timing Diagram/Waveforms x
2.2.2.1. Common Port Mux Interface Waveform 2.2.2.2. Common Port Demux Interface Waveform 2.2.2.3. Controlled Port Mux Interface Waveform 2.2.2.4. Controlled Port Demux Interface Waveform 2.2.2.5. Uncontrolled Port RX Interface Waveform 2.2.2.6. Uncontrolled Port TX Interface Waveform 2.2.2.7. Crypto RX Waveform 2.2.2.8. Crypto TX Waveform 2.2.2.9. MACsec Management Interface (Read) 2.2.2.10. MACsec Management Interface (Write)
3. Parameters x
3.1. MACsec Intel FPGA IP Parameter Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Reset Transactions 4.5. MACsec Software Initialization Sequence
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
5. Functional Description x
5.1. AXI-ST Common/Controlled/Uncontrolled Ports 5.2. Packet Parser and Classifier 5.3. SA Lookup and Update 5.4. Encryption Framer/DeFramer 5.5. Decryption Framer/Deframer 5.6. Packet Aggregator/Disaggregator 5.7. Cryptographic AES 5.8. Error Handling 5.9. Packet Statistics
5.1. AXI-ST Common/Controlled/Uncontrolled Ports x
5.1.1. AXI-ST Single Packet Mode 5.1.2. AXI-ST Multi Packet Mode 5.1.3. User Interface Data Streaming 5.1.4. AXI-ST Ready Latency 5.1.5. Port and Secure Channel Mapping 5.1.6. Port and Crypto Channel Mapping 5.1.7. Minimum Packet Size 5.1.8. Byte Ordering 5.1.9. Controlled/Uncontrolled Port Muxing
5.1.3. User Interface Data Streaming x
5.1.3.1. Single Packet Mode Data Stream 5.1.3.2. Multi Packet Mode Data Stream
5.2. Packet Parser and Classifier x
5.2.1. Packet Parser 5.2.2. Packet Classifier
5.3. SA Lookup and Update x
5.3.1. Packet Actions 5.3.2. Packet Buffer 5.3.3. New Channel Assignment 5.3.4. Anti-Replay Protection
5.3.1. Packet Actions x
5.3.1.1. Packet Encrypt 5.3.1.2. Packet Decrypt 5.3.1.3. Packet Discard 5.3.1.4. PDU Validation
5.4. Encryption Framer/DeFramer x
5.4.1. Channel Allocation 5.4.2. Packet Framer 5.4.3. VLAN Tagging
5.4.2. Packet Framer x
5.4.2.1. Bypass Packet 5.4.2.2. Stream Interleaving
5.4.3. VLAN Tagging x
5.4.3.1. No VLAN Tag 5.4.3.2. VLAN Tag (Not in Clear) 5.4.3.3. VLAN Tag (Clear)
5.5. Decryption Framer/Deframer x
5.5.1. XPN Recovery 5.5.2. Replay Check Update 5.5.3. Packet Deframer
5.6. Packet Aggregator/Disaggregator x
5.6.1. Packet Aggregator 5.6.2. Packet Disaggregator
5.7. Cryptographic AES x
5.7.1. Register Address Ordering 5.7.2. Byte Order Swapping 5.7.3. Byte Ordering
5.8. Error Handling x
5.8.1. Packet Error Handling 5.8.2. Memory Blocks ECC Errors 5.8.3. Crypto Errors 5.8.4. System-Level Errors
7. MACsec Intel® FPGA IP Example Design x
7.1. Simulation Requirements 7.2. Steps to Run Simulation 7.3. Port Configurations 7.4. Multi Interface Buffering Muxing/Demuxing 7.5. 2x25 GbE (Encryption + Decryption) 7.6. Packet Generator/Checker 7.7. Clocking
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Functional Description
6. Configuration Registers for MACsec IP
7. MACsec Intel® FPGA IP Example Design
8. MACsec Intel FPGA IP User Guide Archives
9. Document Revision History for the MACsec Intel FPGA IP User Guide

3.1. MACsec Intel FPGA IP Parameter Settings

Table 23.  MACsec IP Parameter Settings
Parameter Supported Values Default Settings Parameter Description
Topology Tab
Snapshot Enable Enable, Disable Disable Snapshot Enable for Statistics Counters.
Control Port
  • ENCRYPT_DECRYPT
  • ENCRYPT_ONLY
  • DECRYPT_ONLY
 ENCRYPT_DECRYPT

Controlled ports for encryption and decryption lanes.
Uncontrolled Port Enable Enable, Disable Enable Indicates whether the uncontrolled ports for both transmit and receive lanes are enabled to receive user traffic. When disabled, the uncontrolled ports are hidden from the user.
Number of TX+RX Ports 1-64 4 The number of Controlled Ports supported in MACsec for all ports and streams. In ENCRYPT_DECRYPT mode, the number of TX ports always equals the number of RX ports.
Interface Property Tab
Port VLAN Clear Enable, Disable Enable Defines whether VLLAN Clear is supported for Port X.
User Data Width
  • 256
  • 512
 512 Width of data bus inside the MACsec IP's Port MUX & DEMUX blocks. This indicates the width of data after being muxed which is coming into the MACsec IP and the width of data before demuxing and being sent out of the MACsec IP. Supported values are 256 and 512.
Metadata Enable Enable, Disable Disable Indicates there is user metadata which is tagged along with incoming/outgoing packets into the MACsec IP. Required to support PTP use case.
Port-Specific Settings
Select Port 0-64 0 Selects the port for which parameters are to be configured.
Port Data Width
  • 64
  • 128
  • 256
  • 512
 64 Width of the AXI-ST data ports at the edge of the MACsec IP as presented to the MUX and DEMUX blocks. This indicates the width of AXI-ST data ports before being muxed which is coming into the MACsec IP and the width of data after demuxing and being sent out of the MACsec IP. Supported values are 64, 128, 256, and 512.
Arbiter Ready Latency 0-16 0 Mux/Demux per-port ready latency on the AXI-ST ports at the edge of the MACsec IP. Defines the association between assertion of the READY signal and the corresponding VALID on the Port Mux/Demux and MACsec SIP interface.
802_1AE-2018 Options Tab
Validate Frames Strict, Check, Disable, Null Strict Indicates the transmitted/received frames check level.
Protect Frames Enable, Disable Enable Frames Protection Enable
Replay Protect Enable, Disable Enable Enables Anti-Replay Protection check on packets which go through the RX path.
XPN Mode Enable, Disable Enable Indicates whether the 64b Extended Packet Number is supported.
Example Designs Tab
Example Design Files
Example Design:
  • 1x25G
  • 4x25G
  • 1x100G
 1x25G Selects the supported example design to be generated.

Acknowledgement:

The example design generates with only the Example Design Options specified in the drop-down menu. No other IP parameters that you specify applies to the example design generation.

Checked, Unchecked Unchecked Required to be checked to generate an example design. When checked, you acknowledge that the example design generates with ONLY the Example Design options specified in the drop-down menu, and that no other IP parameters which you specify apply to the generated Example Design.
Generated HDL Format
General file format Verilog Verilog HDL format of generated files.
Level Two Title