MACsec Intel® FPGA IP User Guide

ID 736108
Date 4/03/2023
Public

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6.1.3.1. Single Packet Mode Data Stream

The example below shows the user interface data stream into the MACsec IP as a single full packet in Single Packet Mode. This packet originates from port/stream 0 (based on TID). All the data payload on this example belongs to the same packet. The start of packet in cycle 0 and end of packet in cycle 5 can be derived through the TLAST, Tuser_last_segment<N> and TKEEP signals.
Table 34.  Single Packet Mode with Single Full Packet
AXI-ST Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
TID (TID[5:0]) 0 0 0 0 0 0
TVALID 1 1 1 1 1 1
TLAST 0 0 0 0 0 1
TKEEP All 1 All 1 All 1 All 1 All 1 All 1
Tuser_last_segment<N> (N from 7 to 0) All 0 All 0 All 0 All 0 All 0 All 0
TDATA Data Data Data Data Data Data
The example below shows 3 packets interleaved on the user interface streaming data into the MACsec IP. These packets originate from port/stream 0, 2, and 3 (based on TID) and interleaving happens every 64B word. The packet from port/stream 0 enters the MACsec IP in cycle 0 and 4, and the packet from port/stream 2 enters the MACsec IP in cycle 1, 3, and 6 while the packet from port/stream 3 enters the MACsec IP in cycle 2 and 5. The start and end of packet for each packet can be derived through the TLAST, Tuser_last_segment<N> and TKEEP signals. In this scenario, the start of packet for packet from port/stream 0, 2, and 3 happens in cycle 0, 1, and 2, while the end of packet for packet from port/stream 0, 2, and 3 happens in cycle 4, 5, and 6.
Table 35.  Single Packet Mode with Multiple Packets Interleaved
AXI-ST Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6
TID (TID[5:0]) 0 2 3 2 0 3 2
TVALID 1 1 1 1 1 1 1
TLAST 0 0 0 0 1 1 1
TKEEP All 1 All 1 All 1 All 1 All 1 All 1 All 1
Tuser_last_segment<N> (N from 7 to 0) All 0 All 0 All 0 All 0 All 0 All 0 All 0
TDATA Data Data Data Data Data Data Data