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1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204B Design Example
4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide
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2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
The F-Tile JESD204B Intel® FPGA IP design examples for Intel Agilex® 7 devices feature a simulating testbench.
You can generate the F-Tile JESD204B design examples through the IP catalog in the Quartus® Prime Pro Edition software.
Figure 1. Development Stages for the Design Example