F-Tile JESD204B IP

The generated design example is a self-contained system with its own JESD204B IP core instantiation that is separate from the IP core that is generated from the IP tab. The JESD204B IP base core and PHY layer connect to System Console through the Avalon® memory-mapped interconnect. The JESD204B IP core uses three separate Avalon® memory-mapped ports:

• Base core TX data path—for accessing the TX CSR
• Base core RX data path—for accessing the RX CSR
• PHY layer—for accessing the transceiver PHY CSR

The structure of the design example varies depending on the values of these JESD204B IP core parameters:

• Data path:
  • Duplex—both TX and RX data paths and CSR interfaces present
  • Transmitter—only TX data path and CSR interface present
  • Receiver—only RX data path and CSR interface present

F-Tile Reference and System PLL Clocks IP

The F-Tile Reference and System PLL Clocks IP must be instantiated for designs utilizing F-Tile transceiver PHY operating in system clocking mode.

Each system PLL can use any one of eight FGT reference clocks.

The system PLL instantiated in the design example is configured to run all available lanes at data rate/20 frequency, the same frequency as the native PMA clocking rate. The system PLL shares the same reference clock with the transceiver PLL reference clock.

Reset Sequencers

The reset sequencer is a standard Platform Designer component in the IP Catalog standard library. The reset sequencer generates the following system resets to reset various modules in the system:

1. Core PLL reset—resets the core PLL
2. TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core CSRs
3. TX/RX JESD204B IP MAC and Tile reset—resets the TX/RX JESD204B IP core base module and the Tile
4. TX/RX link reset—resets the TX/RX transport layer link interface
5. TX/RX frame reset—resets the TX/RX transport layer, upstream and downstream modules

The reset sequencer has hard and soft reset options. The hard reset port connects to the global reset input pin in the top level design. The soft reset is activated via Parallel I/O's Avalon® memory-mapped interface by TCL scripts (System Console control). When you assert a hard or soft reset, the reset sequencer cycles through all the various module resets based on a pre-set sequence. The figure below illustrates the sequence and also shows how the reset sequencer output ports correspond to the modules that are being reset.

Two reset sequencers are used for independent TX and RX resets. The following tables show the reset sequencer input output port connections.

1. Reset Release Intel FPGA IP deasserts the nINIT_DONE when the FPGA enters user mode.
2. The deasserted global_rst_n releases the example design reset. The mgmt_rst_in_n deasserts the reset input of reset sequencers.
3. The core PLL (IOPLL) resets are released.
4. When the core PLL is locked, the JESD204B IP CSR resets (jesd204_tx/rx_avs_rst_n) are released and start CSR configuration.
5. For the transmitter, when the CSR configuration is done, the core PLL is locked and the IP reset handshake indicates jesd204_tx_rst_ack_n==0, release JESD204B TX reset, jesd204_tx_rst_n.
6. The jesd204_tx_rst_ack_n asserts to 1 when the TX tile is out of reset.
7. Finally, the JESD204B IP asserts jesd204_tx_out_of_reset==1. The design example's txlink_rst_n and txframe_rst_n are released. The transport layer assembler and pattern generator are now active. The Avalon® streaming interface data transfer begins when JESD204B IP is ready.
8. For the receiver, when CSR configuration is done, the core PLL is locked and the IP reset handshake indicates jesd204_rx_rst_ack_n==0, release JESD204B RX reset, jesd204_rx_rst_n.
9. The jesd204_rx_rst_ack_n asserts to 1 when the RX tile is out of reset.
10. Finally, the JESD204B IP asserts jesd204_rx_out_of_reset==1. The design example's rxlink_rst_n and rxframe_rst_n are released. The transport layer deassembler and pattern checker are now active. The jesd204_rx_link_valid asserts when the link is valid.
11. Anytime you want to reset the design example, the reset can be applied through the PIO soft reset (hw_rst) or global_rst_n. The reset must be asserted when jesd204_tx_rst_ack_n and jesd204_rx_rst_ack_n are asserted to 1. Asserting the reset puts the core PLL, JESD204B IP, and design example components into the reset state.

Avalon® Memory-Mapped Bridge

All the Avalon® memory-mapped submodules in the JESD204B subsystem are connected via Avalon® memory-mapped interconnect to a single Avalon® memory-mapped bridge. This bridge is the single interface for Avalon® memory-mapped communications into and out of the subsystem.

JTAG to Avalon® Master Bridge

The JTAG-to- Avalon® memory-mapped interface master bridge provides a connection between the JTAG host to access the memory-mapped JESD204B IP, F-Tile PMA, PIO control and status, Reset Sequencer control, and SPI Master module.

When the Avalon® memory-mapped interface domain is operating at the mgmt_clk domain, the mgmt_clk is required to be 2x faster than JTAG clock. The mgmt_clk is set to be 100 Mhz in this design example.

For the bridges to successfully transform the incoming streams of bytes to Avalon® memory-mapped interface transactions, the streams of bytes must be constructed according to the protocols used by the cores.

The following figure shows how a bytestream changes through the different layers in the bridges.

JESD204B Platform Designer Address Map

Access the address map of the submodules in the JESD204B subsystem by clicking on the Address Map tab in the Platform Designer window. You can access the Avalon® memory-mapped interface slaves through the following address map.