F-Tile JESD204B Intel® FPGA IP Design Example User Guide

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ID 729497
Date 12/02/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide 2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204B Design Example 4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Simulating the Design Example Testbench x
2.4.1. Simulation Testbench
3. Detailed Description for the F-Tile JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. F-Tile JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204B Design Example
4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide

2.3.2. Directory Structure

The F-Tile JESD204B design example directories contain the generated files for the design examples.
Figure 3. Directory Structure for F-Tile JESD204B Design Example
Table 6.  Directory Files
Directory/File Description
ed_sim The folder that contains simulation testbench files.
ed_sim/models The folder that contains the testbench and source files.
ed_sim/models/pattern The folder that contains the source files for the pattern generator/checker.
ed_sim/models/transport_layer The folder that contains the source files for the transport layer.
ed_sim/setup_scripts The folder that contains the test flow setup scripts.
ed_sim/xcelium The folder that contains the test flow run scripts for Xcelium* Parallel simulator. Also serves as the working directory for the simulator.
ed_sim/mentor The folder that contains the test flow run scripts for ModelSim* or QuestaSim* simulator. Also serves as the working directory for the simulator.
ed_sim/aldec The folder that contains the test flow run scripts for Aldec Riviera-PRO* simulator. Also serves as the working directory for the simulator.
ed_sim/synopsys/vcs The folder that contains the test flow run scripts for VCS* simulator. Also serves as the working directory for the simulator.
ed_sim/synopsys/vcsmx The folder that contains the test flow run scripts for VCS* MX simulator. Also serves as the working directory for the simulator.
ed_synth The folder that contains design example synthesizable components.
ed_synth/intel_s10_user_rst_clkgate_0 The folder that contains the Platform Designer-generated modules of the Reset Release IP.
ed_synth/intel_jesd204_se_outbuf_1bit The folder that contains the Platform Designer-generated modules of the bidirectional I/O buffer for the 3-wire SPI interface.
ed_synth/ip The folder that contains Platform Designer-instantiated IP modules.
ed_synth/jesd_f_ed_qsys_<data path> The folder that contains Platform Designer-generated modules from the jesd_f_ed_qsys_<data path>.qsys system.
ed_synth/jesd_f_ss_<data path> The folder that contains Platform Designer-generated modules from the jesd_f_ss_<data path>.qsys system.
ed_synth/pattern The folder that contains the source files for the pattern generator/checker.
ed_synth/transport_layer The folder that contains the source files for the transport layer.

ed_synth/intel_jesd204b_f_ed_<data path>.qpf

ed_synth/intel_jesd204b_f_ed_<data path>.qsf

Quartus® Prime project and settings files
ed_synth/jesd_f_ed_qsys_<data path>.qsys Platform Designer top level system
ed_synth/jesd_f_ss_<data path>.qsys Platform Designer subsystem
ed_synth/intel_jesd204b_f_ed_<data path>.sv Top level HDL source file
ed_synth/intel_jesd204b_f_ed_<data path>.sdc Top level design constraints file
Level Two Title