F-Tile JESD204B Intel® FPGA IP Design Example User Guide

Download PDF
ID 729497
Date 12/02/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide 2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204B Design Example 4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.4. Simulating the Design Example Testbench x
2.4.1. Simulation Testbench
3. Detailed Description for the F-Tile JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. F-Tile JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the F-Tile JESD204B Intel Agilex® 7 FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204B Design Example
4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide

3.3. Design Example Clock and Reset

The main reference clocks for the design example are refclk_core and refclk_xcvr. These clocks must be supplied from a single external source (i.e refclk_core and refclk_xcvr must be synchronous to one another). The refclk_core is the reference clock for the core PLL and the refclk_xcvr is the reference clock for the TX/RX transceiver PHY. The core PLL generates the link_clk and frame_clk from refclk_core.

The link_clk clocks the F-Tile JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks the transport layer, test pattern generator and checker modules, and any downstream modules. An external source supplies a clock called the mgmt_clk to clock the Avalon® memory-mapped interface interfaces of Platform Designer components.

Table 17.  Design Example Clocks
Clock Description Source Modules Clocked
refclk_core Reference clock for core PLL External Core PLL.
refclk_xcvr Reference clock for F-Tile FGT PMA QUAD and System PLL External F-Tile FGT PMA QUAD and system PLL.
link_clk Link layer clock refclk_core JESD204B IP core link layer, transport layer link interface.
frame_clk Frame layer clock refclk_core Transport layer, test pattern generator and checker, downstream modules.
mgmt_clk Control plane clock External 100 MHz clock.
spi_SCLK SPI serial clock Internal Driven by the master to slaves, to synchronize the data bits.
sysclk System PLL clock External Hard IP EMIB crossing. Generated from F-Tile system PLL IP.
Table 18.  Design Example Resets
Signal Direction Description
global_rst_n Input Global reset for all blocks except JTAG-to- Avalon® memory-mapped interface master bridge. Signal is debounced internally in the design example.
ninit_done Internal Output from Reset Release Intel® FPGA IP for the JTAG-to- Avalon® memory-mapped interface master bridge. Deassert only when the FPGA enter user mode.
hw_rst Internal Active high reset. Reset assertion/deassertion control from bit [30] of PIO control. It asserts mgmt_rst_in_n.
mgmt_rst_in_n Internal Active low reset. Assert when either global_rst_n or hw_rst assert. It reset all Avalon® memory-mapped interface interfaces of various IPs as well as the 2 reset sequencers.
core_pll_rst Internal Active high reset. Reset for core PLL. It's sequenced via reset sequencer 0. It asserts when mgmt_rst_in_n is asserted.
jesd204_tx_avs_rst_n Internal Active low reset. Reset the IP TX Avalon® memory-mapped interface interface. It's sequenced via reset sequencer 0. It asserts when mgmt_rst_in_n is asserted.
jesd204_rx_avs_rst_n Internal Active low reset. Reset the IP RX Avalon® memory-mapped interface interface. It's sequenced via reset sequencer 1. It asserts when mgmt_rst_in_n is asserted.
jesd204_tx_rst_n Internal Active low reset. Reset the JESD204B TX link and tile. It's sequenced via reset sequencer 0. It asserts when mgmt_rst_in_n is asserted.
jesd204_rx_rst_n Internal Active low reset. Reset the JESD204B RX link and tile. It's sequenced via reset sequencer 1. It asserts when mgmt_rst_in_n is asserted.
jesd204_tx_rst_ack_n Internal Reset handshakes signal with jesd204_tx_rst_n.
jesd204_rx_rst_ack_n Internal Reset handshakes signal with jesd204_rx_rst_n.
Level Two Title