1.1. Example Design Details
The example design has a pipelined counter placed in the design solely for you to quickly verify that the Signal Tap connection works. Signal Tap taps this counter so that you can verify the JTAG remote debugging connection is working as expected. If your JTAG remote debugging connections works as expected, you will see the repetitive counters in the Signal Tap capture. The last steps in Running the Remote Debugging Over a PCIe Interface Example Design provide screen captures of the expected output.
Hardware Design
This example design is based on an Intel® Stratix® 10 GX FPGA Development Kit seated into a PCIe x16 slot in a host system running a Linux operating system that is supported by Intel® Quartus® Prime Pro Edition Version 21.3 (or later).
FPGA Device Side
This FPGA device side of the example design is kept relatively simple with the Avalon® memory mapped agent interface of the JTAG-Over-Protocol Intel FPGA IP connected directly to the Avalon® memory mapped host interface of the L-Tile Avalon® Memory Mapped Intel FPGA IP for PCIe. This connection allows the PCIe interface to communicate with the internal JTAG connections of the FPGA device that communicate with the debug logic on the device.
This design uses PCIe BAR4 for communication.
A PLL is used to lower the PCIe external application clock speed down to 50 MHz for the JTAG-Over-Protocol Intel FPGA IP because the recommended speed for the IP is 100 MHz or lower.
To provide some recognizable data in the Signal Tap capture, the example design contains a counter.
Host Machine Side
The host machine side of the PCIe link uses open source application code (etherlink application) along with the open source Linux uio_pci_generic driver. The JTAG server can then send information back and forth across the PCIe link established between the host and FPGA card.