| Updated for: |
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| Intel® Quartus® Prime Design Suite 21.3 |
The JTAG remote debugging example design shows how you can use the JTAG-Over-Protocol Intel FPGA IP in a remote debug solution where the host and FPGA device are connected over a PCIe interface. You can use this example as a reference for developing your own design.
The JTAG-Over-Protocol Intel® FPGA IP gives you access to JTAG debugging on the FPGA device without a physical connection to the JTAG pins on the device. The IP requires additional infrastructure to communicate with the JTAG server. Because system designs often differ, you must create this additional infrastructure to account for your system design.
For more information about the JTAG-Over-Protocol Intel FPGA IP, refer to AN 971: JTAG-Over-Protocol Intel® FPGA IP .
This application source code is available at https://github.com/altera-opensource/remote-debug-for-intel-fpga.
This driver is typically available by default.
In the example design, debugging applications (like Signal Tap ) run on the host machine and communicate with the JTAG server on the same machine. The etherlink application listens to the JTAG server and converts TCP/IP data into PCIe MMIO transactions that are sent to the FPGA device where the PCIe MMIO transactions are forwarded to the JTAG-Over-Protocol (JOP) Intel FPGA IP over an Avalon® Memory-Mapped interface. The JOP IP translates the communication it receives from the JTAG server into JTAG signals for the FPGA debug logic. Debug data is sent back to the JTAG server and debug application in the reverse of this flow.
You can download the JTAG remote debugging over a PCIe interface example design from the Intel® FPGA Design Store.