AN 971: JTAG-Over-Protocol Intel FPGA IP

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ID 728673
Date 6/14/2022
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Document Table of Contents
Document Table of Contents x
1. JTAG-Over-Protocol Intel® FPGA IP Overview 2. JTAG-Over-Protocol Intel® FPGA IP Parameters 3. JTAG-Over-Protocol Intel® FPGA IP Communication with JTAG Server 4. AN 971: JTAG-Over-Protocol Intel FPGA IP Archives 5. AN 971: JTAG-Over-Protocol Intel FPGA IP Revision History
3. JTAG-Over-Protocol Intel® FPGA IP Communication with JTAG Server x
3.1. Etherlink Application TCP/IP Protocol
1. JTAG-Over-Protocol Intel® FPGA IP Overview
2. JTAG-Over-Protocol Intel® FPGA IP Parameters
3. JTAG-Over-Protocol Intel® FPGA IP Communication with JTAG Server
4. AN 971: JTAG-Over-Protocol Intel FPGA IP Archives
5. AN 971: JTAG-Over-Protocol Intel FPGA IP Revision History

3. JTAG-Over-Protocol Intel® FPGA IP Communication with JTAG Server

Because the JTAG-Over-Protocol (JOP) Intel® FPGA IP has an Avalon® memory-mapped interface and the JTAG server communicates over a TCP/IP interface, some infrastructure to convert TCP/IP communication to Avalon® memory-mapped transactions is needed to facilitate the communication between the JOP IP and JTAG server.

The design of this infrastructure depends on your system level design.

As part of your design, you can take advantage of the open source etherlink application that takes TCP/IP communication from the JTAG server and uses Linux open source userspace I/O (UIO) device drivers to forward the data to the FPGA devices. The etherlink application is available from the following GitHub repository:

Depending on your system level design, you might need to customize the etherlink application or develop your own solution.

For an example of a remote debug solution that uses the etherlink application, refer to AN 972: JTAG Remote Debugging Over PCIe Interfaces Example Design .


Section Content
Etherlink Application TCP/IP Protocol

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