Use the JTAG-Over-Protocol (JOP) Intel® FPGA IP to communicate with the internal JTAG debug hardware of an FPGA device through an Avalon® memory-mapped interface instead of the standard JTAG pins connection. You can create a debug host connection to an FPGA device without requiring a physical connection to the FPGA JTAG pins.

By skipping the physical connection, you remove the need for physical JTAG pin access, which can potentially increase the security of your device.

The debugging solution enabled by the JOP Intel® FPGA IP works by having the JOP IP reside on the FPGA device while communicating with a JTAG server that runs on the host machine. Based on the communication with the JTAG server, the JOP IP generates JTAG signals to communicate with internal FPGA device debug hardware.

Any Intel® Quartus® Prime Pro Edition debug application that uses JTAG communication (like Signal Tap Logic Analyzer) can take advantage of this solution. This IP is supported on all Intel FPGA device families that Intel® Quartus® Prime Pro Edition supports.

The JTAG server and the JOP IP are not directly connected to each other. You must create the communication infrastructure between the two. This custom communication infrastructure is sometimes referred to as a universal transport link.

Because you design the communication infrastructure, using the JOP IP can help you develop a remote debug solution for your designs that is tailored to your environment.

Reference designs that enable communication over a PCIe interface, HPS peripherals, or with a Nios® V core are available to help you get started developing your communication infrastructure.