The JESD204C Intel® FPGA IP is instantiated in Duplex mode but only the receiver path is used. For FCLK_MULP =1, WIDTH_MULP = 8, S = 1, the core PLL generates a 375 MHz link clock and a 375 MHz frame clock.

An Intel Agilex® 7 I-Series F-Tile Demo Board is used with the ADI AD9081-FMCA-EBZ EVM connected to the FMC+ connector of the development board. The hardware setup for the ADC interoperability test is shown in the Hardware Setup figure.

• The AD9081-FMCA-EBZ EVM derives power from Intel Agilex® 7 I-Series F-Tile Demo Board through FMC+ connector.
• The F-Tile transceiver and JESD204C Intel® FPGA IP core PLL reference clocks are supplied by Si5345-D-EVB through SMA to SMP cable. Set MUX_DIP_SW0 to high on Intel Agilex® 7 I-Series F-Tile Demo Board to ensure U22 is taking CLKIN1 that is connected to the SMP cable.
• The Si5345-D-EVB provides a reference clock to the HMC7044 programmable clock generator present in the AD9081 EVM through SMP to SMP cable.
• The management clock for JESD204C Intel® FPGA IP core is supplied by Silicon Labs Si5332 programmable clock generator present in the Intel Agilex® 7 I-Series F-Tile Demo Board.
• The HMC7044 programmable clock generator provides the AD9081 device reference clock. The phase-locked loop (PLL) present in the AD9081 device generates the desired ADC sampling clock from the device reference clock.
• For Subclass 1, the HMC7044 clock generator generates the SYSREF signal for the AD9081 device and for the JESD204C Intel® FPGA IP through the FMC+ connector.