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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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7.3.7.2. Updating an Application Image
The Add Application-1 Image, Option 5 performs RSU Image update by adding Application-1 image into RSU slot 1, called App-1. It reads the Application-1 RPD image from the QSPI flash, starting from address 0x3000000. After the RPD image is read successfully, the software proceeds to add and verify the configuration bitstream into App-1 slot. Once the verification completes, you can proceed to trigger reconfiguration with Application-1 Image in the table Trigger Device Reconfiguration.
Application Image Update Log
Reading the Application-1 image based on RPD memory map.... Read Successfully. Slot App-1 created at 0x1800000 with size = 0x460000 bytes. Slot 1 is erased. NAME: App-1 OFFSET: 0x0000000001800000 SIZE: 0x00460000 PRIORITY: [disabled] Slot 1 was programmed with size=4587520. Slot 1 was verified with size=4587520. Add and Verify the image successfully in Slot 1 Please proceed with Option 4 - Trigger reconfiguration to Application Images. And select Application-1 Image.