Nios® V Embedded Processor Design Handbook

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ID 726952
Date 1/27/2025
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Document Table of Contents
Document Table of Contents x
1. About the Nios® V Embedded Processor 2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer 3. Nios® V Processor Software System Design 4. Nios® V Processor Configuration and Booting Solutions 5. Nios® V Processor - Using the MicroC/TCP-IP Stack 6. Nios® V Processor Debugging, Verifying, and Simulating 7. Nios® V Processor — Remote System Update 8. Nios® V Processor — Using Custom Instruction 9. Nios® V Embedded Processor Design Handbook Archives 10. Document Revision History for the Nios® V Embedded Processor Design Handbook
1. About the Nios® V Embedded Processor x
1.1. Intel® FPGA and Embedded Processors Overview 1.2. Quartus® Prime Software Support 1.3. Nios® V Processor Licensing 1.4. Embedded System Design
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer x
2.1. Creating Nios® V Processor System Design with Platform Designer 2.2. Integrating Platform Designer System into the Quartus® Prime Project 2.3. Designing a Nios® V Processor Memory System 2.4. Clocks and Resets Best Practices 2.5. Assigning a Default Agent 2.6. Assigning a UART Agent for Printing 2.7. JTAG Signals
2.1. Creating Nios® V Processor System Design with Platform Designer x
2.1.1. Instantiating Nios® V Processor Intel® FPGA IP 2.1.2. Defining System Component Design 2.1.3. Specifying Base Addresses and Interrupt Request Priorities
2.1.1. Instantiating Nios® V Processor Intel® FPGA IP x
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Intel® FPGA IP 2.1.1.2. Instantiating Nios® V/m Microcontroller Intel® FPGA IP 2.1.1.3. Instantiating Nios® V/g General Purpose Processor Intel® FPGA IP
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Intel® FPGA IP x
2.1.1.1.1. Use Reset Request Tab 2.1.1.1.2. Vectors Tab 2.1.1.1.3. ECC Tab 2.1.1.1.4. CPU Architecture Tab
2.1.1.2. Instantiating Nios® V/m Microcontroller Intel® FPGA IP x
2.1.1.2.1. Debug Tab 2.1.1.2.2. Use Reset Request Tab 2.1.1.2.3. Traps, Exceptions, and Interrupts Tab 2.1.1.2.4. CPU Architecture 2.1.1.2.5. ECC Tab
2.1.1.3. Instantiating Nios® V/g General Purpose Processor Intel® FPGA IP x
2.1.1.3.1. Debug Tab 2.1.1.3.2. Use Reset Request Tab 2.1.1.3.3. Traps, Exceptions, and Interrupts Tab 2.1.1.3.4. Memory Configurations Tab 2.1.1.3.5. Custom Instruction Tab 2.1.1.3.6. CPU Architecture 2.1.1.3.7. ECC Tab 2.1.1.3.8. Lockstep Tab
2.2. Integrating Platform Designer System into the Quartus® Prime Project x
2.2.1. Instantiating the Nios® V Processor System Module in the Quartus® Prime Project 2.2.2. Connecting Signals and Assigning Physical Pin Locations 2.2.3. Constraining the Intel FPGA Design
2.3. Designing a Nios® V Processor Memory System x
2.3.1. Volatile Memory 2.3.2. Non-Volatile Memory 2.3.3. On-Chip Memory Configuration – RAM or ROM 2.3.4. Caches 2.3.5. Tightly Coupled Memory
2.4. Clocks and Resets Best Practices x
2.4.1. System Clock 2.4.2. Reset Request Interface 2.4.3. Reset Release IP
2.4.2. Reset Request Interface x
2.4.2.1. Typical Use Cases
2.6. Assigning a UART Agent for Printing x
2.6.1. Preventing Stalls by the JTAG UART
3. Nios® V Processor Software System Design x
3.1. Nios V Processor Software Development Flow 3.2. Intel FPGA Embedded Development Tools
3.1. Nios V Processor Software Development Flow x
3.1.1. Board Support Package Project 3.1.2. Application Project
3.2. Intel FPGA Embedded Development Tools x
3.2.1. Nios® V Processor Board Support Package Editor 3.2.2. RiscFree* IDE for Intel FPGAs 3.2.3. Nios V Utilities Tools 3.2.4. File Format Conversion Tools 3.2.5. Other Utilities Tools
4. Nios® V Processor Configuration and Booting Solutions x
4.1. Introduction 4.2. Linking Applications 4.3. Nios® V Processor Booting Methods 4.4. Introduction to Nios® V Processor Booting Methods 4.5. Nios® V Processor Booting from On-Chip Flash (UFM) 4.6. Nios® V Processor Booting from General Purpose QSPI Flash 4.7. Nios® V Processor Booting from Configuration QSPI Flash 4.8. Nios® V Processor Booting from On-Chip Memory (OCRAM) 4.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM) 4.10. Summary of Nios® V Processor Vector Configuration and BSP Settings 4.11. Reducing Nios® V Processor Booting Time
4.2. Linking Applications x
4.2.1. Linking Behavior
4.2.1. Linking Behavior x
4.2.1.1. Default BSP Linking 4.2.1.2. Configurable BSP Linking
4.4. Introduction to Nios® V Processor Booting Methods x
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash 4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier 4.4.3. Nios® V Processor Application Execute-In-Place from OCRAM 4.4.4. Nios® V Processor Application Execute-In-Place from TCM
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash x
4.4.1.1. alt_load()
4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier x
4.4.2.1. Nios® V Processor Bootloader via Generic Serial Flash Interface 4.4.2.2. Nios® V Processor Bootloader via Secure Device Manager
4.5. Nios® V Processor Booting from On-Chip Flash (UFM) x
4.5.1. MAX® 10 FPGA On-Chip Flash Description 4.5.2. Nios® V Processor Application Execute-In-Place from UFM 4.5.3. Nios® V Processor Application Copied from UFM to RAM using Boot Copier
4.5.2. Nios® V Processor Application Execute-In-Place from UFM x
4.5.2.1. Hardware Design Flow 4.5.2.2. Software Design Flow 4.5.2.3. Programming
4.5.3. Nios® V Processor Application Copied from UFM to RAM using Boot Copier x
4.5.3.1. Hardware Design Flow 4.5.3.2. Software Design Flow 4.5.3.3. Programming
4.6. Nios® V Processor Booting from General Purpose QSPI Flash x
4.6.1. Nios® V Processor Application Executes-In-Place from General Purpose QSPI Flash 4.6.2. Nios® V Processor Application Copied from General Purpose QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI)
4.6.1. Nios® V Processor Application Executes-In-Place from General Purpose QSPI Flash x
4.6.1.1. Hardware Design Flow 4.6.1.2. Software Design Flow 4.6.1.3. Programming Files Generation 4.6.1.4. QSPI Flash Programming
4.6.2. Nios® V Processor Application Copied from General Purpose QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) x
4.6.2.1. Hardware Design Flow 4.6.2.2. Software Design Flow 4.6.2.3. Programming Files Generation 4.6.2.4. QSPI Flash Programming
4.7. Nios® V Processor Booting from Configuration QSPI Flash x
4.7.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash 4.7.2. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) 4.7.3. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
4.7.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash x
4.7.1.1. Hardware Design Flow 4.7.1.2. Software Design Flow 4.7.1.3. Programming Files Generation 4.7.1.4. QSPI Flash Programming
4.7.2. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) x
4.7.2.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) 4.7.2.2. Bootloader via GSFI Example Design
4.7.2.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) x
4.7.2.1.1. Hardware Design Flow 4.7.2.1.2. Software Design Flow 4.7.2.1.3. Programming Files Generation 4.7.2.1.4. QSPI Flash Programming
4.7.3. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices) x
4.7.3.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via SDM) 4.7.3.2. Bootloader via SDM Example Design
4.7.3.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via SDM) x
4.7.3.1.1. Hardware Design Flow 4.7.3.1.2. Software Design Flow 4.7.3.1.3. Software Design Flow (Bootloader via SDM Project) 4.7.3.1.4. Software Design Flow (User Application Project) 4.7.3.1.5. Programming Files Generation 4.7.3.1.6. QSPI Flash Programming SDM
4.8. Nios® V Processor Booting from On-Chip Memory (OCRAM) x
4.8.1. Nios® V Processor Application Executes in-place from OCRAM
4.8.1. Nios® V Processor Application Executes in-place from OCRAM x
4.8.1.1. Hardware Design Flow 4.8.1.2. Software Design Flow 4.8.1.3. Programming
4.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM) x
4.9.1. Nios® V Processor Application Executes in-place from TCM
4.9.1. Nios® V Processor Application Executes in-place from TCM x
4.9.1.1. Hardware Design Flow 4.9.1.2. Software Design Flow 4.9.1.3. Programming
4.11. Reducing Nios® V Processor Booting Time x
4.11.1. Boot Methods 4.11.2. Boot devices 4.11.3. Peripheral Initialization 4.11.4. Caches 4.11.5. System Speed
5. Nios® V Processor - Using the MicroC/TCP-IP Stack x
5.1. Introduction 5.2. Software Architecture 5.3. Support and Licensing 5.4. MicroC/TCP-IP Example Designs 5.5. Development Flow 5.6. Operating the Example Designs 5.7. Optional Configuration 5.8. MicroC/TCP-IP Simple Socket Server Concepts
5.4. MicroC/TCP-IP Example Designs x
5.4.1. Hardware and Software Requirements 5.4.2. Overview 5.4.3. Acquiring the Example Design Files 5.4.4. Hardware Design Files 5.4.5. Software Design Files
5.4.5. Software Design Files x
5.4.5.1. MicroC/TCP-IP IPerf Example Design 5.4.5.2. MicroC/TCP-IP Simple Socket Server Example Design
5.5. Development Flow x
5.5.1. Hardware Development Flow 5.5.2. Software Development Flow 5.5.3. Device Programming
5.5.2. Software Development Flow x
5.5.2.1. Creating a BSP project 5.5.2.2. Configuring the BSP 5.5.2.3. Creating an Application Project 5.5.2.4. Building the Application Project
5.6. Operating the Example Designs x
5.6.1. Operating the MicroC/TCP-IP IPerf 5.6.2. Operating the MicroC/TCP-IP Simple Socket Server
5.7. Optional Configuration x
5.7.1. Configuring Hardware Name 5.7.2. Configuring MAC and IP Addresses 5.7.3. Configuring MicroC/TCP-IP Initialization 5.7.4. Configuring iPerf Server Auto-Initialization
5.7.3. Configuring MicroC/TCP-IP Initialization x
5.7.3.1. Network Task Configuration 5.7.3.2. Network Interface Configuration
5.8. MicroC/TCP-IP Simple Socket Server Concepts x
5.8.1. MicroC/OS-II Resources 5.8.2. Error Handling 5.8.3. MicroC/TCP-IP Stack Default Configuration
6. Nios® V Processor Debugging, Verifying, and Simulating x
6.1. Debugging Nios® V/c Processor 6.2. Debugging Nios® V Processor Hardware Designs 6.3. Debugging Nios® V Processor Software Designs 6.4. Debugging Tools 6.5. Additional Embedded Design Considerations 6.6. Simulating Nios® V Processor Designs
6.1. Debugging Nios® V/c Processor x
6.1.1. Pilot System with Non-pipelined Nios V/m Processor 6.1.2. printf() Debugging
6.2. Debugging Nios® V Processor Hardware Designs x
6.2.1. JTAG Server 6.2.2. System Console 6.2.3. Signal Tap Logic Analyzer 6.2.4. In-System Sources and Probes
6.2.2. System Console x
6.2.2.1. JTAG to Avalon® Host Bridge Core
6.2.3. Signal Tap Logic Analyzer x
6.2.3.1. Hardware and Software Requirements 6.2.3.2. Setting Up Signal Tap Logic Analyzer 6.2.3.3. Running the Capture Session 6.2.3.4. Analyzing Results
6.2.3.2. Setting Up Signal Tap Logic Analyzer x
6.2.3.2.1. Enabling Signal Tap Logic Analyzer 6.2.3.2.2. Adding Signals for Monitoring and Debugging 6.2.3.2.3. Specifying Trigger Conditions 6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode 6.2.3.2.5. Compiling the Design and Programming the Target Device
6.2.3.2.3. Specifying Trigger Conditions x
6.2.3.2.3.1. Basic Trigger Conditions 6.2.3.2.3.2. Power-Up Trigger Conditions 6.2.3.2.3.3. Other Trigger Conditions 6.2.3.2.3.4. No Trigger Conditions
6.2.3.3. Running the Capture Session x
6.2.3.3.1. Performing Data Capture with Ashling* RiscFree* IDE for Intel® FPGAs 6.2.3.3.2. Performing Data Capture Without Software Download
6.2.3.4. Analyzing Results x
6.2.3.4.1. Viewing Data 6.2.3.4.2. Correlating Trace Data to Software ELF 6.2.3.4.3. Saving and Converting Captured Data
6.3. Debugging Nios® V Processor Software Designs x
6.3.1. Ashling* RiscFree* IDE for Intel® FPGAs 6.3.2. OpenOCD 6.3.3. Objdump File 6.3.4. Show Make Commands
6.5. Additional Embedded Design Considerations x
6.5.1. JTAG Signal Integrity 6.5.2. Additional Memory Space for System Prototyping
6.6. Simulating Nios® V Processor Designs x
6.6.1. Prerequisites 6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer 6.6.3. Creating Nios V Processor Software 6.6.4. Generating Memory Initialization File 6.6.5. Generating System Simulation Files 6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer x
6.6.2.1. Using IP and Platform Designer Simulation Setup Scripts
6.6.3. Creating Nios V Processor Software x
6.6.3.1. Generating the Board Support Package 6.6.3.2. Generating the Application Project File 6.6.3.3. Building the Application Project
7. Nios® V Processor — Remote System Update x
7.1. Overview 7.2. Quartus® Prime Pro Edition Software and Tool Support 7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices
7.2. Quartus® Prime Pro Edition Software and Tool Support x
7.2.1. Intel® Quartus® Prime Pro Edition Software 7.2.2. Programming File Generator
7.2.1. Intel® Quartus® Prime Pro Edition Software x
7.2.1.1. Setting Max Retry Parameter 7.2.1.2. Selecting Factory Load Pin
7.2.2. Programming File Generator x
7.2.2.1. Programming File Generator File Types 7.2.2.2. Bitswap Option 7.2.2.3. Quartus® Prime Programmer 7.2.2.4. Supported QSPI Flash Devices
7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices x
7.3.1. Individual Factory, Application, and Update Images 7.3.2. Hardware Design Flow 7.3.3. Software Design Flow 7.3.4. Individual Images Generation 7.3.5. Remote System Update Image Files Generation 7.3.6. QSPI Flash Programming 7.3.7. Operating the RSU Client API
7.3.2. Hardware Design Flow x
7.3.2.1. Create a Platform Designer System 7.3.2.2. Quartus® Prime Software Settings
7.3.3. Software Design Flow x
7.3.3.1. Generating the ZLIB libraries 7.3.3.2. Creating a Board Support Package Project 7.3.3.3. Configuring and Generating the BSP Project 7.3.3.4. Creating Multiple Application Projects 7.3.3.5. Building the Application Projects 7.3.3.6. Generating HEX Files
7.3.5. Remote System Update Image Files Generation x
7.3.5.1. Generating Initial RSU Image Using SOF file 7.3.5.2. Generating an Application Update Image 7.3.5.3. Generating a Factory Update Flash Image
7.3.6. QSPI Flash Programming x
7.3.6.1. Programming the Initial RSU Image 7.3.6.2. Programming the Update Images
7.3.7. Operating the RSU Client API x
7.3.7.1. Trigger Reconfiguration Menu with Selected Image 7.3.7.2. Updating an Application Image 7.3.7.3. Updating the Factory Image
8. Nios® V Processor — Using Custom Instruction x
8.1. Introduction 8.2. Unimplemented Instruction Example Design 8.3. Hardware Acceleration Example Design
8.2. Unimplemented Instruction Example Design x
8.2.1. Hardware and Software Requirements 8.2.2. Overview 8.2.3. Acquiring the Example Design File 8.2.4. Hardware Design Files 8.2.5. Software Design Files 8.2.6. Development Flow 8.2.7. Operating the Example Design
8.2.6. Development Flow x
8.2.6.1. Hardware Development Flow 8.2.6.2. Software Development Flow 8.2.6.3. Device Programming
8.3. Hardware Acceleration Example Design x
8.3.1. Hardware and Software Requirements 8.3.2. Overview 8.3.3. Acquiring the Example Design File 8.3.4. Hardware Design Files 8.3.5. Software Design Files 8.3.6. Development Flow 8.3.7. Operating the Example Design
8.3.6. Development Flow x
8.3.6.1. Hardware Development Flow 8.3.6.2. Software Development Flow 8.3.6.3. Device Programming
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook

4.5.1. MAX® 10 FPGA On-Chip Flash Description

MAX® 10 FPGA devices contain on-chip flash that is segmented into two parts:

  • Configuration Flash Memory (CFM) — stores the hardware configuration data for MAX® 10 FPGAs.
  • User Flash Memory (UFM) — stores the user data or software applications.

The UFM architecture of MAX® 10 device is a combination of soft and hard IPs. You can only access the UFM using the On-Chip Flash IP Core in the Quartus® Prime software.

The On-chip Flash IP core supports the following features:

  • Read or write accesses to UFM and CFM (if enabled in Platform Designer) sectors using the Avalon® MM data and control slave interface.
  • Supports page erase, sector erase and sector write.
  • Simulation model for UFM read/write accesses using various EDA simulation tools.
Table 29.  On-chip Flash Regions in MAX® 10 FPGA Devices
Flash Regions Functionality
Configuration Flash Memory (sectors CFM0-2) FPGA configuration file storage

User Flash Memory

(sectors UFM0-1)

 Nios® V processor application and user data

MAX® 10 FPGA devices support several configuration modes and some of these modes allow CFM1 and CFM2 to be used as an additional UFM region. The following table shows the storage location of the FPGA configuration images based on the MAX® 10 FPGA's configuration modes.

Table 30.  Storage Location of FPGA Configuration Images
Configuration Mode CFM2 CFM1 CFM0
Dual compressed images Compressed Image 2 Compressed Image 1
Single uncompressed image Virtual UFM Uncompressed image
Single uncompressed image with Memory Initialization Uncompressed image (with pre-initialized on-chip memory content)
Single compressed image with Memory Initialization Compressed image (with pre-initialized on-chip memory content)
Single compressed image Virtual UFM Compressed Image

You must use the On-chip Flash IP core to access to the flash memory in MAX® 10 FPGAs. You can instantiate and connect the On-chip Flash IP to the Quartus® Prime software. The Nios® V soft core processor uses the Platform Designer interconnects to communicate with the On-chip Flash IP.

Figure 17. Connection between On-chip Flash IP and Nios® V Processor
Note: Ensure the On-chip Flash csr port is connected to the Nios® V processor data_manager to enable the processor to control write and erase operations.

The On-chip Flash IP core can provide access to five flash sectors - UFM0, UFM1, CFM0, CFM1, and CFM2.

Important information about the UFM and CFM sectors.:

  • CFM sectors are intended for configuration (bitstream) data (*.pof) storage.
  • User data can be stored in the UFM sectors and may be hidden, if the correct settings are selected in the Platform Designer tool.
  • Certain devices do not have a UFM1 sector. You can refer to the table: UFM and CFM Sector Size for available sectors in each individual MAX® 10 FPGA device.
  • You can configure CFM2 as a virtual UFM by selecting Single Uncompressed Image configuration mode.
  • You can configure CFM2 and CFM1 as a virtual UFM by selecting Single Uncompressed Image configuration mode.
  • The size of each sector varies with the selected MAX® 10 FPGA devices.
Table 31.  UFM and CFM Sector SizeThis table lists the dimensions of the UFM and CFM arrays.
Device Pages per Sector Page Size (Kbit) Maximum User Flash Memory Size (Kbit) 3 Total Configuration Memory Size (Kbit) OCRAM Size (Kbit)
UFM1 UFM0 CFM2 CFM1 CFM0
10M02 3 3 0 0 34 16 96 544 108
10M04 0 8 41 29 70 16 1248 2240 189
10M08 8 8 41 29 70 16 1376 2240 378
10M16 4 4 38 28 66 32 2368 4224 549
10M25 4 4 52 40 92 32 3200 5888 675
10M40 4 4 48 36 84 64 5888 10752 1260
10M50 4 4 48 36 84 64 5888 10752 1638
Related Information
3 The maximum possible value, which is dependent on the configuration mode you select.
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