Visible to Intel only — GUID: teu1690858828408
Ixiasoft
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
Visible to Intel only — GUID: teu1690858828408
Ixiasoft
7.3.6.2. Programming the Update Images
- Ensure that the Intel FPGA device’s Active Serial (AS) pin is routed to the QSPI flash. This routing allows the flash loader to load into the QSPI flash and configure the board correctly.
- Ensure the MSEL pin setting on the board is configured for AS programming.
- Open the Intel Quartus Prime Configuration Debugger and make sure JTAG is detected under the Hardware Setup.
- Click Load Device and select the Intel FPGA device.
- Navigate to the Flash tab.
- Click Auto-detect to auto-detect the QSPI Flash that is attached to the device.
- Navigate to the Program function. Assign Image Start Address and RPD file path.
-
For app_image.rpd, the Image Start Address is 0x3000000.
-
For factory_update.rpd, the Image Start Address is 0x3800000.
-
- Click Program RPD to begin.
Figure 135. Configuration Debugger - FlashFigure 136. Quad SPI Flash Address Map
Memory Map File of Initial RSU JIC Image
BLOCK START ADDRESS END ADDRESS BOOT_INFO 0x00000000 0x0010FFFF FACTORY_IMAGE 0x00110000 0x0084FFFF (0x0080CFFF) SPT0 0x00850000 0x00857FFF SPT1 0x00858000 0x0085FFFF CPB0 0x00860000 0x00867FFF CPB1 0x00868000 0x0086FFFF App-0 0x01000000 0x01432FFF Configuration device: 1SX280LU2 Configuration mode: Active Serial x4
Related Information