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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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4.5.1.1.3. Programming Files Generation
JTAG Indirect Configuration File (.jic) Generation
- In the Quartus® Prime software, go to File > Convert Programming Files.
- For Programming file type, select JTAG Indirect Configuration File (.jic)
- For Mode select Active Serial x4.
Figure 29. Convert Programming File Window
- Click “…” to enter the Configuration Device tab and select the available options. The Configuration Device allows for choosing a specific supported device or alternatively an unsupported device.
Figure 30. Configuration Device Window
- If you are using a supported device, make your selection, and click OK. Else, proceed with the following steps:
- Select <<new device>>.
- Enter the information about Device name, Device ID, Device I/O voltage, Device density, Total device die, Dummy clock (Single I/O or Quad I/O mode) and Programming flow template.
- Click Apply.
Note: The Programming flow template helps you define a template for flash operation in Initialization, Program, Erase, Verify/Blank-Check/Examine and Termination. If the device is not available for selection, refer to Modifying Programming Flows in Generic Flash Programmer User Guide to modify the programming flow. For details about memory parameters like dummy clock cycles, please contact the related vendor.
- Under the Input files to convert tab,
- Choose the Flash Loader for the FPGA used by selecting Flash Loader and click Add Device.
- Add the .sof file to the SOF Data by selecting SOF Data and click Add File.
- Click Add Hex Data to add Nios® V application (.hex) file. Select the Absolute addressing and Big-endian button. Browse to the .hex file location. Click OK.
- Click Generate to generate the JIC file.
Figure 31. Input files to convert tab