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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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7.3.1. Individual Factory, Application, and Update Images
The example requires four images to demonstrate the RSU feature. You can modify a Nios® V processor project and create four different systems with distinctive functions. However, you need to perform multiple compilation to achieve that.
To simplify the build flow, this example implements two processor systems (factory and application system) and makes three copies of the latter .SOF file and named them respectively as below:
- factory.sof (Factory Image .SOF)
- application-0.sof (App Image .SOF)
- application-1.sof (App Update Image .SOF)
- application-2.sof (Factory Update Image .SOF)
Even if the application images contain the same bitstreams, you can identify the images using the RSU status log.
System | Factory | Application |
---|---|---|
Platform Designer System | To create a Platform Designer system, follow the steps in section Hardware Design Flow with OCRAM size of 6 Mbytes. | To create a Platform Designer system, follow the steps in section Hardware Design Flow with OCRAM size of 1 Mbytes. |
Board Support Package | Apply the BSP settings using the steps in section Software Design Flow. | |
Nios® V Processor Source Code | Uses factory.c that features basic RSU operations from Example source code for Nios V Processor LibRSU application. Refer to the link in Related Information. | Uses application.c that features a simplified RSU operations from Example source code for Nios V Processor LibRSU application. Refer to the link in Related Information. |
Processor Boot Method | Software boots from OCRAM. |
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