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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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4.7.1.1. Hardware Design Flow
The following sections describe a step-by-step method for building a bootable system for a Nios® V processor application from TCM. The example below is built using Arria® 10 SoC development kit.
IP Component Settings
- Create your Nios® V processor project using Quartus® Prime and Platform Designer.
Figure 80. Connections for Nios® V Processor Project
Note: Place all external peripheral IPs (e.g. JTAG UART, MSGDMA, PIO, and others) within a peripheral region. This requirement does not apply to dm_agent and timer_sw_agent.
TCM Settings for Nios® V Processor
- In the Nios® V processor parameter editor, enable the Instruction TCM1 and Data TCM1.
- Initialize Instruction TCM1 with itcm.hex.
- Initialize Data TCM1 with dtcm.hex.
Figure 81. Instruction TCM1 SettingsFigure 82. Data TCM1 Settings
- Align the base address of instruction_tcs1 to be the same as Instruction ITCM1 (0x40000).
Figure 83. Instruction_tcs1 Aligned Base Address
Reset Agent Settings for Nios® V Processor
- In the Nios® V processor parameter editor, set the Reset Agent to Instruction TCM1.
Figure 84. Reset Agent Settings for Nios® V Processor
- Click Generate HDL, the Generation dialog box appears.
- Specify output file generation options and then click Generate.
Quartus® Prime Settings
- In the Intel Quartus Prime software, click Assignment > Device > Device and Pin Options > Configuration.
- Set Configuration scheme according to your FPGA configuration scheme
- Click OK to exit the Device and Pin Options window.
- Click OK to exit the Device window.
- Click Start Compilation to compile your project.
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