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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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8.2.4. Hardware Design Files
The Agilex™ 7 FPGA - Custom Instruction Design on Nios® V/g Processor is developed using the Platform Designer. You can generate the hardware files using the build_sof.py Python script.
The example design consists of:
- Nios® V Processor Intel® FPGA IP
- On-Chip Memory II Intel® FPGA IP
- JTAG UART Intel® FPGA IP
- Processing Engine 1 (PE1) – Declares funct3 as user-defined intermediate (3’bxxx). All custom operations share a single software C-macro. You can select them using funct3 input argument.
- Processing Engine 2 (PE2) – Defines funct3 as extension index (3’b000 to 3’b111). Each operations have its own C-macros. You can call their respective C-macros.
The processing engine comprises of the following operations, which are selected based on the 3-bits funct3 field.
- Operation 0: 1’s complement of Data0
- Operation 1: 2’s complement of Data0
- Operation 2: Multiply Data0 with Data1
- Operation 3: Bit reversal of Data0
- Operation 4: Byte reversal of Data0
- Operation 5: Word reversal of Data0
- Operation 6: Lower word merge of Data0 and Data1
- Operation 7: Higher word merge of Data0 and Data1
Figure 137. Example Design Block Diagram