Visible to Intel only — GUID: yed1645672163486
Ixiasoft
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
Visible to Intel only — GUID: yed1645672163486
Ixiasoft
5.4.1. Hardware and Software Requirements
To use a µC/OS-II and µC/TCP-IP program on an Intel FPGA requires the following hardware and software:
- Quartus® Prime software
- Quartus® Prime Pro Edition software version 21.3 or later
- Quartus® Prime Standard Edition software version 22.1 or later
- Ashling* RiscFree* IDE for Intel FPGAs software version 22.2 or later
Note: Altera recommends you to install the same software version for all softwares.
- One of the supported Intel FPGA devices
- The example designs are implemented on Arria® 10 10 SoC development kit
- Intel FPGA Download Cable II
- RJ-45 connected Ethernet cable on the same network as the PC development host
You must connect your development board to a host PC on the Ethernet and USB/JTAG ports.
Related Information