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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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7.3.5.1. Generating Initial RSU Image Using SOF file
- On the File menu, click Programming File Generator.
- Select Active Serial x4 from the Configuration mode drop-down list. The current Quartus® Prime software only supports remote system update feature in Active Serial x4.
- On the Output Files tab, assign the output directory and file name.
- Select the output file type as JTAG Indirect Configuration File (.jic) with
- Memory Map File (.map)
- Raw Programming File (.rpd)
By default, the .rpd file type is little-endian. Set the Bit swap to On to generate the .rpd file in big endian format.
Note: If you are using a third-party programmer that does not support the little-endian format, set the Bit swap to On.Figure 127. Programming File Generator (Output Files) - On the Input Files tab, click Add Bitstream, select the factory.sof file and click Open. Repeat this step for the application-0.sof.
Figure 128. Programming File Generator (Input Files)
- On the Configuration Device tab, click Add Device, select your flash memory and click OK. The Programming File Generator tool automatically populates the flash partitions.
- Select the FACTORY_IMAGE partition and click Edit.
- In the Edit Partition dialog box, select the factory.sof file in the Input Files drop-down list and click OK.
Note: You must assign Page 0 to Factory Image. Altera recommends that you let the Quartus® Prime software assign the Start address of the FACTORY_IMAGE automatically by retaining the default value for Address Mode which is Auto.Figure 129. Programming File Generator (Edit Partition)
- Select the flash memory and click Add Partition.
- In the Add Partition dialog box, perform the following steps:
- Define Name as App-0
- Select the application-0.sof file from the Input file drop-down list
- Assign Page 1
- Assign Address Mode as Start with starting address at 0x01000000.
- If you are generating .jic files, click Select at the Flash loader, select your device family and device name, and click OK.
Figure 130. Programming File Generator (Configuration Device)
- Click Generate to generate the remote system update programming files. After generating the programming file, proceed to program the flash memory with the initial RSU image.