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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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7.3.2.1. Create a Platform Designer System
- Add the Nios® V processor and the following peripherals into the Platform Designer system:
- Nios® V/m Processor Intel® FPGA IP
- On-Chip Memory (RAM) Intel® FPGA IP
- JTAG UART Intel® FPGA IP
- Mailbox Client Intel® FPGA IP
- JTAG to Avalon Master Bridge Intel® FPGA IP
Figure 119. Connections in Platform Designer System - In the Nios® V processor Parameters tab
- Enable the Enable Debug feature.
- Set the Reset Agent to OCRAM.
Figure 120. Nios® V Processor Intel® FPGA IP Parameter Editor - In the On-Chip Memory (RAM or ROM) Intel FPGA Parameters tab Total memory size box, specify the memory size as below:
- 1 Mbytes for application system
- 6 Mbytes for factory system.
- Enable Initialize memory content and Enable non-default initialization file with app.hex in the OCRAM.
Figure 121. On-Chip Memory Intel FPGA IP Parameter Editor
- Click Generate HDL, the Generation dialog box appears.
- Specify output file generation options and then click Generate.