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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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7.3.3.3. Configuring and Generating the BSP Project
- In the BSP Editor, go to Main > Settings > Advanced > hal.linker.
- Enable the following settings:
- allow_code_at_reset
- enable_alt_load
- enable_alt_load_copy_rwdata
Figure 125. hal.linker Settings - Navigate to the BSP Linker Script tab in the BSP Editor.
- Set all the Linker Section Name list to the OCRAM.
- In the BSP Drivers, enable the device driver for Mailbox Client Intel® FPGA IP.
- Go to Settings > altera_s10_mailbox_client. You may set rsu_log_level as 0 for minimum logging information.
- Apply rsu_protected_slot as -1 for no slot protection.
- Enable the following settings:
- rsu.enable_spt_checksum
- rsu.enable_rsu
- fpga_device.Stratix10
Note: Select other options for fpga_device when you are not using the Stratix® 10 device.
Figure 126. BSP Drivers Tab - Click Generate BSP. Make sure the BSP generation is successful.
- Close the BSP Editor.