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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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4.5.2.2. Bootloader via SDM Example Design
You can download the Bootloader via SDM example design from the Intel FPGA Design Store. The example design is based on the Stratix® 10 SX SoC L-Tile development kit.
Using the provided scripts, the hardware and software design are generated and programmed respectively as SRAM Object Files (.sof) and JTAG Indirect Configuration Files (.jic) into the device.
Follow the steps below to generate the Bootloader via SDM example design:
- Go to Intel® FPGA Design Store.
- Search for Stratix10 - Bootloader SDM Design package.
- Click on the link at the title.
- Accept the Software License Agreement.
- Download the package according to the Quartus® Prime software version of your host machine.
- Refer to the readme.txt for how-to guide.
File | Description |
---|---|
hw/ | Contains files necessary to run the hardware project. |
ready_to_test/ | Contains pre-built hardware and software binaries to run the design on the target hardware. For this package, the target hardware is Stratix® 10 SX 10 SoC L-tile development kit. |
scripts/ | Consists of scripts to build the design. |
sw/ | Contains software application files. |
readme.txt | Contains description and steps to apply the pre-bulit binaries or rebuild the binaries from scratch. |
Figure 68. Bootloader via SDM Example Design
Figure 69. JUART Terminal Output
- In the beginning, the window displays the following message
- Reaching the end, the window displays the following message: