Nios® V Embedded Processor Design Handbook

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ID 726952
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the Nios® V Embedded Processor 2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer 3. Nios® V Processor Software System Design 4. Nios® V Processor Configuration and Booting Solutions 5. Nios® V Processor - Using the MicroC/TCP-IP Stack 6. Nios® V Processor Debugging, Verifying, and Simulating 7. Nios® V Processor — Remote System Update 8. Nios® V Processor — Using Custom Instruction 9. Nios® V Embedded Processor Design Handbook Archives 10. Document Revision History for the Nios® V Embedded Processor Design Handbook
1. About the Nios® V Embedded Processor x
1.1. Intel® FPGA and Embedded Processors Overview 1.2. Intel® Quartus® Prime Software Support 1.3. Nios® V Processor Licensing 1.4. Embedded System Design 1.5. Nios® V Processor Quick Start Guide
1.5. Nios® V Processor Quick Start Guide x
1.5.1. System Requirements 1.5.2. Nios® V Processor Example Design 1.5.3. Software Design Flow 1.5.4. Programming Nios® V into the FPGA Device
1.5.1. System Requirements x
1.5.1.1. Hardware and Software Requirements
1.5.3. Software Design Flow x
1.5.3.1. Generating the Board Support Package 1.5.3.2. Generating the Application Project File 1.5.3.3. Building the Application Project
1.5.3.1. Generating the Board Support Package x
1.5.3.1.1. Generating the Board Support Package using the BSP Editor GUI 1.5.3.1.2. Generating the Board Support Package using the Command-Line Interface
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer x
2.1. Creating Nios® V Processor System Design with Platform Designer 2.2. Integrating Platform Designer System into the Intel® Quartus® Prime Project 2.3. Designing a Nios® V Processor Memory System 2.4. Clocks and Resets Best Practices 2.5. Assigning a Default Agent
2.1. Creating Nios® V Processor System Design with Platform Designer x
2.1.1. Instantiating Nios® V Processor Intel® FPGA IP 2.1.2. Defining System Component Design 2.1.3. Specifying Base Addresses and Interrupt Request Priorities
2.1.1. Instantiating Nios® V Processor Intel® FPGA IP x
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Intel® FPGA IP 2.1.1.2. Instantiating Nios® V/m Microcontroller Intel® FPGA IP 2.1.1.3. Instantiating Nios® V/g General Purpose Processor Intel® FPGA IP
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Intel® FPGA IP x
2.1.1.1.1. Use Reset Request Tab 2.1.1.1.2. Vectors Tab 2.1.1.1.3. ECC Tab
2.1.1.2. Instantiating Nios® V/m Microcontroller Intel® FPGA IP x
2.1.1.2.1. Debug Tab 2.1.1.2.2. Use Reset Request Tab 2.1.1.2.3. Vectors Tab 2.1.1.2.4. CPU Architecture 2.1.1.2.5. ECC Tab
2.1.1.3. Instantiating Nios® V/g General Purpose Processor Intel® FPGA IP x
2.1.1.3.1. Debug Tab 2.1.1.3.2. Use Reset Request Tab 2.1.1.3.3. Vectors Tab 2.1.1.3.4. Memory Configurations Tab 2.1.1.3.5. Custom Instruction Tab 2.1.1.3.6. CPU Architecture 2.1.1.3.7. ECC Tab
2.2. Integrating Platform Designer System into the Intel® Quartus® Prime Project x
2.2.1. Instantiating the Nios® V Processor System Module in the Intel® Quartus® Prime Project 2.2.2. Connecting Signals and Assigning Physical Pin Locations 2.2.3. Constraining the Intel FPGA Design
2.3. Designing a Nios® V Processor Memory System x
2.3.1. Volatile Memory 2.3.2. Non-Volatile Memory 2.3.3. On-Chip Memory Configuration – RAM or ROM
2.4. Clocks and Resets Best Practices x
2.4.1. Reset Request Interface
2.4.1. Reset Request Interface x
2.4.1.1. Typical Use Cases
3. Nios® V Processor Software System Design x
3.1. Nios V Processor Software Development Flow 3.2. Intel FPGA Embedded Development Tools
3.1. Nios V Processor Software Development Flow x
3.1.1. Board Support Package Project 3.1.2. Application Project
3.2. Intel FPGA Embedded Development Tools x
3.2.1. Nios® V Processor Board Support Package Editor 3.2.2. RiscFree* IDE for Intel FPGAs 3.2.3. Eclipse CDT for Embedded C/C++ Developer 3.2.4. Nios V Utilities Tools 3.2.5. File Format Conversion Tools 3.2.6. Other Utilities Tools
4. Nios® V Processor Configuration and Booting Solutions x
4.1. Introduction 4.2. Linking Applications 4.3. Nios® V Processor Booting Methods 4.4. Introduction to Nios® V Processor Booting Methods 4.5. Nios® V Processor Booting from Configuration QSPI Flash 4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM) 4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM) 4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
4.2. Linking Applications x
4.2.1. Linking Behavior
4.2.1. Linking Behavior x
4.2.1.1. Default BSP Linking 4.2.1.2. Configurable BSP Linking
4.4. Introduction to Nios® V Processor Booting Methods x
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash 4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier 4.4.3. Nios® V Processor Application Execute-In-Place from OCRAM 4.4.4. Nios® V Processor Application Execute-In-Place from TCM
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash x
4.4.1.1. alt_load()
4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier x
4.4.2.1. GSFI Bootloader 4.4.2.2. SDM Bootloader
4.5. Nios® V Processor Booting from Configuration QSPI Flash x
4.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) 4.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
4.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) x
4.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash 4.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) 4.5.1.3. GSFI Bootloader Example Design
4.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash x
4.5.1.1.1. Hardware Design Flow 4.5.1.1.2. Software Design Flow 4.5.1.1.3. Programming Files Generation 4.5.1.1.4. QSPI Flash Programming
4.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) x
4.5.1.2.1. Hardware Design Flow 4.5.1.2.2. Software Design Flow 4.5.1.2.3. Programming Files Generation 4.5.1.2.4. QSPI Flash Programming
4.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices) x
4.5.2.1. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader) 4.5.2.2. SDM Bootloader Example Design
4.5.2.1. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader) x
4.5.2.1.1. Hardware Design Flow 4.5.2.1.2. Software Design Flow 4.5.2.1.3. Software Design Flow (SDM Bootloader Project) 4.5.2.1.4. Software Design Flow (User Application Project) 4.5.2.1.5. Programming Files Generation 4.5.2.1.6. QSPI Flash Programming SDM
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM) x
4.6.1. Nios® V Processor Application Executes in-place from OCRAM
4.6.1. Nios® V Processor Application Executes in-place from OCRAM x
4.6.1.1. Hardware Design Flow 4.6.1.2. Software Design Flow 4.6.1.3. Programming
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM) x
4.7.1. Nios® V Processor Application Executes in-place from TCM
4.7.1. Nios® V Processor Application Executes in-place from TCM x
4.7.1.1. Hardware Design Flow 4.7.1.2. Software Design Flow 4.7.1.3. Programming
5. Nios® V Processor - Using the MicroC/TCP-IP Stack x
5.1. Introduction 5.2. Software Architecture 5.3. Support and Licensing 5.4. MicroC/TCP-IP Example Designs 5.5. Development Flow 5.6. Operating the Example Designs 5.7. Optional Configuration 5.8. MicroC/TCP-IP Simple Socket Server Concepts
5.4. MicroC/TCP-IP Example Designs x
5.4.1. Hardware and Software Requirements 5.4.2. Overview 5.4.3. Acquiring the Example Design Files 5.4.4. Hardware Design Files 5.4.5. Software Design Files
5.4.5. Software Design Files x
5.4.5.1. MicroC/TCP-IP IPerf Example Design 5.4.5.2. MicroC/TCP-IP Simple Socket Server Example Design
5.5. Development Flow x
5.5.1. Hardware Development Flow 5.5.2. Software Development Flow 5.5.3. Device Programming
5.5.2. Software Development Flow x
5.5.2.1. Creating a BSP project 5.5.2.2. Configuring the BSP 5.5.2.3. Creating an Application Project 5.5.2.4. Building the Application Project
5.6. Operating the Example Designs x
5.6.1. Operating the MicroC/TCP-IP IPerf 5.6.2. Operating the MicroC/TCP-IP Simple Socket Server
5.7. Optional Configuration x
5.7.1. Configuring Hardware Name 5.7.2. Configuring MAC and IP Addresses 5.7.3. Configuring MicroC/TCP-IP Initialization 5.7.4. Configuring iPerf Server Auto-Initialization
5.7.3. Configuring MicroC/TCP-IP Initialization x
5.7.3.1. Network Task Configuration 5.7.3.2. Network Interface Configuration
5.8. MicroC/TCP-IP Simple Socket Server Concepts x
5.8.1. MicroC/OS-II Resources 5.8.2. Error Handling 5.8.3. MicroC/TCP-IP Stack Default Configuration
6. Nios® V Processor Debugging, Verifying, and Simulating x
6.1. Debugging Nios® V/c Processor 6.2. Debugging Nios® V Processor Software Designs 6.3. Debugging Tools 6.4. Additional Embedded Design Considerations 6.5. Simulating Nios® V Processor Designs
6.1. Debugging Nios® V/c Processor x
6.1.1. Steps to Debug Nios® V/c Processor
6.2. Debugging Nios® V Processor Software Designs x
6.2.1. OpenOCD and Eclipse Embedded CDT 6.2.2. Objdump File 6.2.3. Show Make Commands
6.4. Additional Embedded Design Considerations x
6.4.1. JTAG Signal Integrity 6.4.2. Additional Memory Space for System Prototyping
6.5. Simulating Nios® V Processor Designs x
6.5.1. Prerequisites 6.5.2. Setting Up and Generating Your Simulation Environment in Platform Designer 6.5.3. Creating Nios V Processor Software 6.5.4. Generating Memory Initialization File 6.5.5. Generating System Simulation Files 6.5.6. Running Simulation in the QuestaSim Simulator Using Command Line
6.5.2. Setting Up and Generating Your Simulation Environment in Platform Designer x
6.5.2.1. Using IP and Platform Designer Simulation Setup Scripts
6.5.3. Creating Nios V Processor Software x
6.5.3.1. Generating the Board Support Package 6.5.3.2. Generating the Application Project File 6.5.3.3. Building the Application Project
7. Nios® V Processor — Remote System Update x
7.1. Overview 7.2. Intel® Quartus® Prime Pro Edition Software and Tool Support 7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices
7.2. Intel® Quartus® Prime Pro Edition Software and Tool Support x
7.2.1. Intel® Quartus® Prime Pro Edition Software 7.2.2. Programming File Generator
7.2.1. Intel® Quartus® Prime Pro Edition Software x
7.2.1.1. Setting Max Retry Parameter 7.2.1.2. Selecting Factory Load Pin
7.2.2. Programming File Generator x
7.2.2.1. Programming File Generator File Types 7.2.2.2. Bitswap Option 7.2.2.3. Intel® Quartus® Prime Programmer 7.2.2.4. Supported QSPI Flash Devices
7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices x
7.3.1. Individual Factory, Application, and Update Images 7.3.2. Hardware Design Flow 7.3.3. Individual Images Generation 7.3.4. Remote System Update Image Files Generation 7.3.5. QSPI Flash Programming 7.3.6. Operating the RSU Client API
7.3.2. Hardware Design Flow x
7.3.2.1. Create a Platform Designer System 7.3.2.2. Intel® Quartus® Prime Software Settings 7.3.2.3. Software Design Flow
7.3.2.3. Software Design Flow x
7.3.2.3.1. Generating the ZLIB libraries 7.3.2.3.2. Creating a Board Support Package Project 7.3.2.3.3. Configuring and Generating the BSP Project 7.3.2.3.4. Creating Multiple Application Projects 7.3.2.3.5. Building the Application Projects 7.3.2.3.6. Generating HEX Files
7.3.4. Remote System Update Image Files Generation x
7.3.4.1. Generating Initial RSU Image Using SOF file 7.3.4.2. Generating an Application Update Image 7.3.4.3. Generating a Factory Update Flash Image
7.3.5. QSPI Flash Programming x
7.3.5.1. Programming the Initial RSU Image 7.3.5.2. Programming the Update Images
7.3.6. Operating the RSU Client API x
7.3.6.1. Trigger Reconfiguration Menu with Selected Image 7.3.6.2. Updating an Application Image 7.3.6.3. Updating the Factory Image
8. Nios® V Processor — Using Custom Instruction x
8.1. Introduction 8.2. Unimplemented Instruction Example Design 8.3. Hardware Acceleration Example Design
8.2. Unimplemented Instruction Example Design x
8.2.1. Hardware and Software Requirements 8.2.2. Overview 8.2.3. Acquiring the Example Design File 8.2.4. Hardware Design Files 8.2.5. Software Design Files 8.2.6. Development Flow 8.2.7. Operating the Example Design
8.2.6. Development Flow x
8.2.6.1. Hardware Development Flow 8.2.6.2. Software Development Flow 8.2.6.3. Device Programming
8.3. Hardware Acceleration Example Design x
8.3.1. Hardware and Software Requirements 8.3.2. Overview 8.3.3. Acquiring the Example Design File 8.3.4. Hardware Design Files 8.3.5. Software Design Files 8.3.6. Development Flow 8.3.7. Operating the Example Design
8.3.6. Development Flow x
8.3.6.1. Hardware Development Flow 8.3.6.2. Software Development Flow 8.3.6.3. Device Programming
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook

5.4.4. Hardware Design Files

Despite the example designs functioned differently, they share similar hardware design and BSP settings. The only difference lies in their respective Nios V application source code, one for the Simple Socket Server application, while the other for the iPerf 2 application.

The µC/TCP-IP example designs are developed using the Platform Designer. The hardware files can be generated using the build_sof.py Python script. The example design consist of:

  • Nios® V Processor Intel FPGA IP
  • On-Chip Memory II Intel FPGA IP for System Memory and Descriptor Memory
  • JTAG UART Intel FPGA IP
  • System ID Peripheral Intel FPGA IP
  • Parallel I/O Intel FPGA IP (PIO)
  • Modular Scatter-Gather DMA Intel FPGA IP (mSGDMA)
  • Triple-Speed Ethernet Intel FPGA IP (TSE)
Figure 93. Hardware Block Diagram
Note:
  • (1) The first n bytes are reserved for mSGDMA descriptor buffers, where n is the number of bytes taken by the configured RX or TX buffers. Applications must not use this memory region.
  • (2) For MAC variations without internet FIFO buffers, the transmit and receive FIFOs are external to the MAC function.
  • (3) Only one buffer type (RX or TX buffers) can reside in the descriptor memory.
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