Nios® V Embedded Processor Design Handbook

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Date 9/01/2023
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Document Table of Contents
Document Table of Contents x
1. About the Nios® V Embedded Processor 2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer 3. Nios® V Processor Software System Design 4. Nios® V Processor Configuration and Booting Solutions 5. Nios® V Processor - Using the MicroC/TCP-IP Stack 6. Nios® V Processor Debugging, Verifying, and Simulating 7. Nios® V Processor — Remote System Update 8. Nios® V Processor — Using Custom Instruction 9. Nios® V Embedded Processor Design Handbook Archives 10. Document Revision History for the Nios® V Embedded Processor Design Handbook
1. About the Nios® V Embedded Processor x
1.1. Intel® FPGA and Embedded Processors Overview 1.2. Intel® Quartus® Prime Software Support 1.3. Embedded System Design 1.4. Nios® V Processor Quick Start Guide
1.4. Nios® V Processor Quick Start Guide x
1.4.1. System Requirements 1.4.2. Nios® V/m Processor Example Design 1.4.3. Software Design Flow 1.4.4. Programming Nios® V/m into the FPGA Device
1.4.1. System Requirements x
1.4.1.1. Hardware and Software Requirements
1.4.3. Software Design Flow x
1.4.3.1. Generating the Board Support Package 1.4.3.2. Generating the Application Project File 1.4.3.3. Building the Application Project
1.4.3.1. Generating the Board Support Package x
1.4.3.1.1. Generating the Board Support Package using the BSP Editor GUI 1.4.3.1.2. Generating the Board Support Package using the Command-Line Interface
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer x
2.1. Creating Nios® V Processor System Design with Platform Designer 2.2. Integrating Platform Designer System into the Intel® Quartus® Prime Project 2.3. Designing a Nios® V Processor Memory System 2.4. Clocks and Resets Best Practices 2.5. Assigning a Default Agent
2.1. Creating Nios® V Processor System Design with Platform Designer x
2.1.1. Instantiating Nios® V/m Processor Intel® FPGA IP 2.1.2. Defining System Component Design 2.1.3. Specifying Base Addresses and Interrupt Request Priorities
2.1.1. Instantiating Nios® V/m Processor Intel® FPGA IP x
2.1.1.1. Configure Nios® V Processor Parameters
2.1.1.1. Configure Nios® V Processor Parameters x
2.1.1.1.1. Debug Tab 2.1.1.1.2. Use Reset Request Tab 2.1.1.1.3. Vectors Tab 2.1.1.1.4. Caches and Peripheral Regions Tab 2.1.1.1.5. Custom Instruction Tab
2.2. Integrating Platform Designer System into the Intel® Quartus® Prime Project x
2.2.1. Instantiating the Nios® V Processor System Module in the Intel® Quartus® Prime Project 2.2.2. Connecting Signals and Assigning Physical Pin Locations 2.2.3. Constraining the Intel FPGA Design
2.3. Designing a Nios® V Processor Memory System x
2.3.1. Volatile Memory 2.3.2. Non-Volatile Memory 2.3.3. On-Chip Memory Configuration – RAM or ROM
2.4. Clocks and Resets Best Practices x
2.4.1. Reset Request Interface
2.4.1. Reset Request Interface x
2.4.1.1. Typical Use Cases
3. Nios® V Processor Software System Design x
3.1. Nios V Processor Software Development Flow 3.2. Intel FPGA Embedded Development Tools
3.1. Nios V Processor Software Development Flow x
3.1.1. Board Support Package Project 3.1.2. Application Project
3.2. Intel FPGA Embedded Development Tools x
3.2.1. Nios® V Processor Board Support Package Editor 3.2.2. RiscFree* IDE for Intel FPGAs 3.2.3. Eclipse CDT for Embedded C/C++ Developer 3.2.4. Nios V Utilities Tools 3.2.5. File Format Conversion Tools 3.2.6. Other Utilities Tools
4. Nios® V Processor Configuration and Booting Solutions x
4.1. Introduction 4.2. Linking Applications 4.3. Nios® V Processor Booting Methods 4.4. Introduction to Nios® V Processor Booting Methods 4.5. Nios® V Processor Booting from Configuration QSPI Flash 4.6. Nios V Processor Booting from On-Chip Memory (OCRAM) 4.7. Summary of Nios® V Processor Vector Configuration and BSP Settings
4.2. Linking Applications x
4.2.1. Linking Behaviour
4.2.1. Linking Behaviour x
4.2.1.1. Default BSP Linking 4.2.1.2. Configurable BSP Linking
4.4. Introduction to Nios® V Processor Booting Methods x
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash 4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier 4.4.3. Nios® V Processor Application Execute-In-Place from OCRAM
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash x
4.4.1.1. alt_load()
4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier x
4.4.2.1. GSFI Bootloader 4.4.2.2. SDM Bootloader
4.5. Nios® V Processor Booting from Configuration QSPI Flash x
4.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) 4.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
4.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) x
4.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash 4.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) 4.5.1.3. GSFI Bootloader Example Design
4.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash x
4.5.1.1.1. Hardware Design Flow 4.5.1.1.2. Software Design Flow 4.5.1.1.3. Programming Files Generation 4.5.1.1.4. QSPI Flash Programming
4.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) x
4.5.1.2.1. Hardware Design Flow 4.5.1.2.2. Software Design Flow 4.5.1.2.3. Programming Files Generation 4.5.1.2.4. QSPI Flash Programming
4.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices) x
4.5.2.1. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader) 4.5.2.2. SDM Bootloader Example Design
4.5.2.1. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader) x
4.5.2.1.1. Hardware Design Flow 4.5.2.1.2. Software Design Flow 4.5.2.1.3. Software Design Flow (SDM Bootloader Project) 4.5.2.1.4. Software Design Flow (User Application Project) 4.5.2.1.5. Programming Files Generation 4.5.2.1.6. QSPI Flash Programming SDM
4.6. Nios V Processor Booting from On-Chip Memory (OCRAM) x
4.6.1. Nios V Processor Application Executes in-place from OCRAM
4.6.1. Nios V Processor Application Executes in-place from OCRAM x
4.6.1.1. Hardware Design Flow 4.6.1.2. Software Design Flow 4.6.1.3. Programming
5. Nios® V Processor - Using the MicroC/TCP-IP Stack x
5.1. Introduction 5.2. Software Architecture 5.3. Support and Licensing 5.4. MicroC/TCP-IP Example Designs 5.5. Development Flow 5.6. Operating the Example Designs 5.7. Optional Configuration 5.8. MicroC/TCP-IP Simple Socket Server Concepts
5.4. MicroC/TCP-IP Example Designs x
5.4.1. Hardware and Software Requirements 5.4.2. Overview 5.4.3. Acquiring the Example Design Files 5.4.4. Hardware Design Files 5.4.5. Software Design Files
5.4.5. Software Design Files x
5.4.5.1. MicroC/TCP-IP IPerf Example Design 5.4.5.2. MicroC/TCP-IP Simple Socket Server Example Design
5.5. Development Flow x
5.5.1. Hardware Development Flow 5.5.2. Software Development Flow 5.5.3. Device Programming
5.5.2. Software Development Flow x
5.5.2.1. Creating a BSP project 5.5.2.2. Configuring the BSP 5.5.2.3. Creating an Application Project 5.5.2.4. Building the Application Project
5.6. Operating the Example Designs x
5.6.1. Operating the MicroC/TCP-IP IPerf 5.6.2. Operating the MicroC/TCP-IP Simple Socket Server
5.7. Optional Configuration x
5.7.1. Configuring Hardware Name 5.7.2. Configuring MAC and IP Addresses 5.7.3. Configuring MicroC/TCP-IP Initialization 5.7.4. Configuring iPerf Server Auto-Initialization
5.7.3. Configuring MicroC/TCP-IP Initialization x
5.7.3.1. Network Task Configuration 5.7.3.2. Network Interface Configuration Default network interface configuration in uc_tcp_ip_init.c
5.8. MicroC/TCP-IP Simple Socket Server Concepts x
5.8.1. MicroC/OS-II Resources 5.8.2. Error Handling 5.8.3. MicroC/TCP-IP Stack Default Configuration
6. Nios® V Processor Debugging, Verifying, and Simulating x
6.1. Debugging Nios® V Processor Software Designs 6.2. Debugging Tools 6.3. Additional Embedded Design Considerations 6.4. Simulating Nios® V Processor Designs
6.1. Debugging Nios® V Processor Software Designs x
6.1.1. OpenOCD and Eclipse Embedded CDT 6.1.2. Objdump File 6.1.3. Show Make Commands
6.3. Additional Embedded Design Considerations x
6.3.1. JTAG Signal Integrity 6.3.2. Additional Memory Space for System Prototyping
6.4. Simulating Nios® V Processor Designs x
6.4.1. Prerequisites 6.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer 6.4.3. Creating Nios V Processor Software 6.4.4. Generating Memory Initialization File 6.4.5. Generating System Simulation Files 6.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
6.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer x
6.4.2.1. Using IP and Platform Designer Simulation Setup Scripts
6.4.3. Creating Nios V Processor Software x
6.4.3.1. Generating the Board Support Package 6.4.3.2. Generating the Application Project File 6.4.3.3. Building the Application Project
7. Nios® V Processor — Remote System Update x
7.1. Overview 7.2. Intel® Quartus® Prime Pro Edition Software and Tool Support 7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices
7.2. Intel® Quartus® Prime Pro Edition Software and Tool Support x
7.2.1. Intel® Quartus® Prime Pro Edition Software 7.2.2. Programming File Generator
7.2.1. Intel® Quartus® Prime Pro Edition Software x
7.2.1.1. Setting Max Retry Parameter 7.2.1.2. Selecting Factory Load Pin
7.2.2. Programming File Generator x
7.2.2.1. Programming File Generator File Types 7.2.2.2. Bitswap Option 7.2.2.3. Intel® Quartus® Prime Programmer 7.2.2.4. Supported QSPI Flash Devices
7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices x
7.3.1. Individual Factory, Application, and Update Images 7.3.2. Hardware Design Flow 7.3.3. Individual Images Generation 7.3.4. Remote System Update Image Files Generation 7.3.5. QSPI Flash Programming 7.3.6. Operating the RSU Client API
7.3.2. Hardware Design Flow x
7.3.2.1. Create a Platform Designer System 7.3.2.2. Intel® Quartus® Prime Software Settings 7.3.2.3. Software Design Flow
7.3.2.3. Software Design Flow x
7.3.2.3.1. Generating the ZLIB libraries 7.3.2.3.2. Creating a Board Support Package Project 7.3.2.3.3. Configuring and Generating the BSP Project 7.3.2.3.4. Creating Multiple Application Projects 7.3.2.3.5. Building the Application Projects 7.3.2.3.6. Generating HEX Files
7.3.4. Remote System Update Image Files Generation x
7.3.4.1. Generating Initial RSU Image Using SOF file 7.3.4.2. Generating an Application Update Image 7.3.4.3. Generating a Factory Update Flash Image
7.3.5. QSPI Flash Programming x
7.3.5.1. Programming the Initial RSU Image 7.3.5.2. Programming the Update Images
7.3.6. Operating the RSU Client API x
7.3.6.1. Trigger Reconfiguration Menu with Selected Image 7.3.6.2. Updating an Application Image 7.3.6.3. Updating the Factory Image
8. Nios® V Processor — Using Custom Instruction x
8.1. Introduction 8.2. Example Design on Unimplemented Instruction (Custom Instruction Design on Nios® V/g processor) 8.3. Development Flow 8.4. Operating the Example Design
8.2. Example Design on Unimplemented Instruction (Custom Instruction Design on Nios® V/g processor) x
8.2.1. Hardware and Software Requirements 8.2.2. Overview 8.2.3. Acquiring the Example Design File 8.2.4. Hardware Design Files 8.2.5. Software Design Files
8.3. Development Flow x
8.3.1. Hardware Development Flow 8.3.2. Software Development Flow 8.3.3. Device Programming
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook

5.7.3.2. Network Interface Configuration

µC/TCP-IP stores received and transmitted data in network buffers (also referred as receive buffers and transmit buffers). The size of these network buffers should fulfill the minimum and maximum packet frame sizes of the network interfaces.

Based on the µC/TCP-IP application requirements, configure the network buffers to better suit your needs in software/app/uc_tcp_ip_init.c source code. The following are the configurable network buffers:
  • Receive Large Buffer
  • Transmit Large Buffer
  • Transmit Small Buffer

While it is best to leave the size of large buffers at maximum frame size, you can lower the size of the small buffers to reduce the system's RAM usage, further improving the system performance. Additionally, you can configure the number of receive and transmit buffers allocated to the device. Keep in mind that you need to have at least one buffer given for each network.

After configuring the network buffers, register them to a valid memory locations, either the main system memory or a dedicated descriptor memory. If you are using a dedicated descriptor memory, define the starting address and memory span of the descriptor memory in the source code.

Refer to Network Buffers Configuration Table for the µC/TCP-IP example designs default configuration. A dedicated descriptor memory is provided in the hardware system, and registered to the receive buffers. Transmit buffers are routed to the main memory.

Note: Intel recommends receive buffers to hold up to the maximum frame size because the size of data received is unknown to the device. Alternatively, the size of data transmitted is known to the device, making it possible to use small transmit buffers when the transmitted data is smaller than the maximum frame size. Thus, allowing receive buffers to use large buffers only, while transmit buffers use both large and small buffers.
Table 26.  Network Buffers Configuration
Settings Description Default Value
.RxBufPoolType Memory location for the receive data buffers. 6 7 NET_IF_MEM_TYPE_DEDICATED
.RxBufLargeNbr Number of receive buffers allocated to the device. NUM_RX_BUFFERS 8
.TxBufPoolType Memory location for the transmit data buffers. 6 7 NET_IF_MEM_TYPE_MAIN
.TxBufLargeNbr Number of transmit buffers allocated to the device. 5u
.TxBufSmallSize Size of the small transmit buffers. 60u
.TxBufSmallNbr Number of small transmit buffers allocated to the device. 5u
.MemAddr Starting address of the dedicated descriptor memory.9 SYS_DESC_MEM_BASE
.MemSize Size of the dedicated descriptor memory (in bytes). SYS_DESC_MEM_SPAN

Default network interface configuration in uc_tcp_ip_init.c 

static const CPU_INT08U NUM_RX_LISTS = 2;
static const NET_BUF_QTY NUM_RX_BUFFERS =
    2 * NUM_RX_LISTS * ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE;

static NET_DEV_CFG_ETHER NetDev_Cfg_Ether_TSE = {

    .RxBufPoolType    = NET_IF_MEM_TYPE_DEDICATED,
    .RxBufLargeSize   = 1536u,
    .RxBufLargeNbr    = NUM_RX_BUFFERS,
    .RxBufAlignOctets = 4u,
    .RxBufIxOffset    = 2u,

    .TxBufPoolType    = NET_IF_MEM_TYPE_MAIN,
    .TxBufLargeSize   = 1518u,
    .TxBufLargeNbr    = 5u,
    .TxBufSmallSize   = 60u,
    .TxBufSmallNbr    = 5u,
    .TxBufAlignOctets = 4u,
    .TxBufIxOffset    = 0u,

    .MemAddr    = SYS_DESC_MEM_BASE,
    .MemSize    = SYS_DESC_MEM_SPAN,

    .Flags =  NET_DEV_CFG_FLAG_NONE,

    .RxDescNbr = 8u, // NOTE: Not configurable.
    .TxDescNbr = 1u, // NOTE: Not configurable.
    
    .BaseAddr           = 0,
    .DataBusSizeNbrBits = 0,

    .HW_AddrStr = "",
};
6 This field must be set to either NET_IF_MEM_TYPE_MAIN for main memory or NET_IF_MEM_TYPE_DEDICATED for dedicated descriptor memory.
7 Only one buffer type (receive or transmit buffers) can be set to NET_IF_MEM_TYPE_DEDICATED.
8 This field is derived based on NUM_RX_LISTS and ALTERA_TSE_MSGDMA_RX_DESC_CHAIN_SIZE.
9 If there is no dedicated descriptor memory in the system, this field should be set to NULL
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