1.6. F-Tile Ethernet Multirate Intel FPGA IP v6.0.0
Quartus® Prime Version | Description | Impact |
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23.1 | Updated Interface attributes for production silicon. | IP upgrade is required. |
Added new parameter: Enable dedicated CDR Clock Output | Enables recovered CDR clock output for SyncE applications. | |
Added new parameter: Include Deterministic Latency Interface | When enabled, generates the deterministic latency interface ports in FlexE mode. |
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Intel Agilex FPGAs renamed to Agilex™ 7 FPGAs. | — |