F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description 2.4.3. Hardware Testing 2.4.4. Signal
2.4.3. Hardware Testing x
2.4.3.1. Parallel loopback 2.4.3.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

2.2. Hardware and Software Requirements

Intel uses the following hardware and software to test the design example:

Hardware

  • Agilex I-Series SOC Development Kit
  • SDI Signal Generator
  • SDI Signal Analyzer
  • BNC to BNC cables
  • VIDIOTM FMC Development Module VIDIO-12G-A (Nextera 12G SDI FMC daughter card)

Software

  • Intel® Quartus® Prime (software version 22.1 or 21.4 Patch 0.01)
    • Note: Patch only needed for software version 21.4
  • Either one of the following simulators for functional simulation:
    • ModelSim* - Intel® FPGA Edition
    • Questa*-Intel® FPGA Edition
    • VCS* / VCS* MX
    • Xcelium*
Related Information
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