F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 8/05/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Debugging Features
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer(Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = ON) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System 3.8.2. HDMI RX PHY 3.8.3. HDMI TX PHY 3.8.4. RX-TX Link
3.9. Hardware Setup x
3.9.1. Support additional video resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

3.8.1. Platform Design System

Signal Direction Width Description
cpu_clk_in_clk_clk input 1 CPU clock. The frequency is 100 Mhz
axi4s_clk_clk input 1 Clock to AXI4-stream video interface. This clock is 225 Mhz
cpu_rst_in_reset_reset input 1 CPU reset
redriver_i2c_master_sda_in input 1 I2C master interface to configure the external redriver setting
redriver_i2c_master_scl_in input 1
redriver_i2c_master_sda_oe output 1
redriver_i2c_master_scl_oe output 1
txclk_i2c_master_sda_in input 1 I2C master interface to configure the programmable oscillator to output TX video clock for RX-TX retransmit without video frame buffer design
txclk_i2c_master_scl_in input 1
txclk_i2c_master_sda_oe output 1
txclk_i2c_master_scl_oe output 1
hdmi_rx_i2c_clk_clk input 1 Clock input for DDC and SCDC interface. This clock is 100 Mhz
hdmi_rx_i2c_interface_scl input 1 HDMI RX DDC and SCDC interface
hdmi_rx_i2c_interface_sda input 1
hdmi_rx_hpd_interface_in_5v_power input 1 HDMI RX 5V detect and hotplug detect. Refer to Sink Interfaces section in HDMI Intel FPGA IP User Guide for more information
hdmi_rx_hpd_interface_hpd output 1
hdmi_rx_phy_interface_vid_clk input 1 Video clock input
hdmi_rx_phy_interface_rx_clk input 4 Clock out recovered from the RX transceiver. Refer to the Clocking Scheme Signals (RX PHY Clock Out 2) table for more details
hdmi_rx_phy_interface_frl_clk input 1 Clock to FRL path on the RX core. Refer to Section 5.5 FRL Clocking Scheme of HDMI Intel FPGA IP Core User Guide for more details
hdmi_rx_phy_interface_scdc_frl_locked output 4

HDMI RX core data, status and control ports.

Refer to Sink Interfaces section in HDMI Intel FPGA IP Core User Guide for more information

hdmi_rx_phy_interface_scdc_frl_rate output 4
hdmi_rx_phy_interface_locked output 1
hdmi_rx_phy_interface_os input 1
hdmi_rx_phy_interface_in_lock input 1
hdmi_rx_phy_interface_tmds_bit_clock_ratio output 1
hdmi_rx_phy_interface_color_depth output 4
hdmi_rx_phy_interface_rx_parallel_data input 160
hdmi_rx_audio_interface_audio_CTS output 20

HDMI RX core audio data, infoframe and metadata, status and control ports.

Refer to Sink Interfaces section in HDMI Intel FPGA IP User Guide for more information

hdmi_rx_audio_interface_audio_N output 20
hdmi_rx_audio_interface_audio_data output 256
hdmi_rx_audio_interface_audio_de output 1
hdmi_rx_audio_interface_audio_info_ai output 48
hdmi_rx_audio_interface_audio_metadata output 165
hdmi_rx_audio_interface_audio_format output 5
hdmi_rx_audio_interface_audio_clk output 1
hdmi_rx_av_mm_aux_out_aux_pkt_data output 72

Auxiliary Memory Interface.

Refer to Sink Interfaces section in HDMI Intel FPGA IP User Guide for more information

hdmi_rx_av_mm_aux_out_aux_pkt_addr output 7
hdmi_rx_av_mm_aux_out_aux_pkt_wr output 1
hdmi_tx_phy_interface_vid_clk input 1 Video clock input
hdmi_tx_phy_interface_tx_clk input 1 Clock out from the TX transceiver. Refer to the Clocking Scheme Signals (TX PHY Clock Out 2) table for more details
hdmi_tx_phy_interface_frl_clk input 1 Clock to FRL path on the TX core. Refer to Section 5.5 FRL Clocking Scheme of HDMI Intel FPGA IP Core User Guide for more details
hdmi_tx_phy_interface_os input 2

HDMI TX core data, status and control ports.

Refer to Section 5.2: Source Interfaces in HDMI Intel FPGA IP Core User Guide for more information

hdmi_tx_phy_interface_scdc_frl_rate output 4
hdmi_tx_phy_interface_tx_parallel_data output 160
hdmi_tx_phy_interface_in_lock input 1
hdmi_tx_hpd_interface_hpd input 1
hdmi_tx_i2c_interface_scl input 1 HDMI TX DDC and SCDC interface
hdmi_tx_i2c_interface_sda input 1
hdmi_tx_audio_interface_audio_clk input 1

HDMI TX core audio data, infoframe and metadata, status and control ports.

Refer to Section 5.3 Source Interfaces in HDMI Intel FPGA IP User Guide for more information

hdmi_tx_audio_interface_audio_CTS input 20
hdmi_tx_audio_interface_audio_N input 20
hdmi_tx_audio_interface_audio_data input 256
hdmi_tx_audio_interface_audio_de input 1
hdmi_tx_audio_interface_audio_mute input 1
hdmi_tx_audio_interface_audio_info_ai input 49
hdmi_tx_audio_interface_audio_metadata input 166
hdmi_tx_audio_interface_audio_format input 5
ddr4_emif_local_reset_req_local_reset_req input 1

External Memory IP Interface (EMIF) for DDR4.

Refer to Section 4.1 of Intel Agilex EMIF IP Interface and Signal Descriptions of External Memory Interface Intel Agilex FPGA IP User Guide for more details

ddr4_emif_local_reset_status_local_reset_done output 1
ddr4_emif_pll_ref_clk_clk input 1
ddr4_emif_oct_oct_rzqin input 1
ddr4_emif_mem_mem_ck output 1
ddr4_emif_mem_mem_ck_n output 1
ddr4_emif_mem_mem_a output 17
ddr4_emif_mem_mem_act_n output 1
ddr4_emif_mem_mem_ba output 2
ddr4_emif_mem_mem_bg output 1
ddr4_emif_mem_mem_cke output 1
ddr4_emif_mem_mem_cs_n output 1
ddr4_emif_mem_mem_odt output 1
ddr4_emif_mem_mem_reset_n output 1
ddr4_emif_mem_mem_par output 1
ddr4_emif_mem_mem_alert_n input 1
ddr4_emif_mem_mem_dqs input 9
ddr4_emif_mem_mem_dqs_n input 9
ddr4_emif_mem_mem_dq input 72
ddr4_emif_mem_mem_dbi_n input 9
ddr4_emif_status_local_cal_success output 1
ddr4_emif_status_local_cal_fail output 1
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