F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 4/11/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter and Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.04.11 23.1 2.0.2
  • Updated Table: Brief Information about the F-Tile JESD204C Intel® FPGA IP
    • Updated description for Core Features
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Performance.
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Parameters:
    • Updated value for Data rate parameter
  • Replaced individual Transmitter Registers and Receiver Registers sections with a new combined Transmitter and Receiver Registers section that provides links to register maps
  • Removed Table: Related Documents
  • Updated the product family name to "Intel Agilex

    7"
2023.02.10 22.2 1.1.0
  • Fixed the links in Table 1: Related Documents.
2022.08.18 22.2 1.1.0
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Performance
2022.06.21 22.2 1.1.0
  • Updated Table: F-Tile JESD204C IP Clocks
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Parameters:
    • Updated value and description for Transceiver type parameter
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Performance:
    • Updated Maximum Data Rate (Gbps) column
  • Updated Table: Top-level Transmitter IP Core Signals
    • Added j204c_syspll_div2_clk port signal
  • Updated Table: Top-level Receiver IP Core Signals
    • Added j204c_syspll_div2_clk port signal
  • Updated topic: F-Tile JESD204C Intel FPGA IP User Guide Archives
2022.04.26 21.4 1.0.0
  • Added Figure: Example Timing Diagram of j204c_txfclk_ctrl when FCLK_MULP=2
  • Updated Table: Top-level Transmitter IP Core Signals
  • Updated Table: Top-level Receiver IP Core Signals
2021.12.13 21.4 1.0.0
  • Added new topics:
    • Multi-Device Synchronization
    • Multi-Device DAC Application for Subclass 1
    • Multi-Device ADC Application for Subclass 1
    • RBD Tuning Mechanism
    • Transceiver Toolkit
  • Added NPDME to Table: Acronym List.
  • Updated Table: Related Documents.
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Parameters:
    • Added a new parameter—Enable debug endpoint for PMA Avalon® memory-mapped interface .
    • Updated parameter name Enable dynamic reconfiguration to Enable PMA Avalon® memory-mapped interface .
  • Updated the following figures:
    • Figure: F-Tile JESD204C Duplex Functional Block Diagram
    • Figure: F-Tile JESD204C RX-only Functional Block Diagram
  • Updated the descriptions and figure in F-Tile JESD204C TX Reset Sequence.
  • Updated the descriptions and figure in F-Tile JESD204C RX Reset Sequence.
  • Updated the description for reconfig_xcvr_clk in Table: Top-level Transmitter IP Core Signals.
  • Added information about reconfig_xcvr_reset in the following tables:
    • Table: Top-level Transmitter IP Core Signals
    • Table: Top-level Receiver IP Core Signals
  • Removed xcvr_pll_locked from Table: Top-level Transmitter IP Core Signals.
  • Updated Deterministic Latency to correct the legal value of RBD count.
  • Corrected the description for F-Tile JESD204C MAC to and from the PHY interface in Table: F-Tile JESD204C Intel® FPGA IP Interfaces to clarity that the IP can generate MAC and PHY configuration.
2021.10.11 21.3 1.0.0 Initial release.
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