| Select Design |
- System Console Control
- None
|
Select the system console control to access the design example data path through the system console. |
| Simulation |
On, Off |
Turn on for the IP to generate the necessary files for simulating the design example. |
| Synthesis |
On, Off |
Turn on for the IP to generate the necessary files for Quartus® Prime compilation and hardware demonstration. |
| HDL format (for simulation) |
|
Select the HDL format of the RTL files for simulation. |
| HDL format (for synthesis) |
Verilog only |
Select the HDL format of the RTL files for synthesis. |
| Generate 3-wire SPI module |
On, Off |
Turn on to enable 3-wire SPI interface instead of 4-wire. |
| Sysref mode |
- One-shot
- Periodic
- Gapped periodic
|
Select whether you want the SYSREF alignment to be a one-shot pulse mode, periodic, or gapped periodic, based on your design requirements and timing flexibility.
- One-shot—Select this option to enable SYSREF to be a one-shot pulse mode. The sysref_ctrl[17] register bit's value is 0. After the F-Tile JESD204C IP reset deasserts, change the sysref_ctrl[17] register's value from 0 to 1, then to 0, for a one-shot SYSREF pulse.
- Periodic—SYSREF in periodic mode has 50:50 duty cycle. SYSREF period is E*SYSREF_MULP.
- Gapped periodic—SYSREF has programmable duty cycle of granularity of 1 link clock cycle. SYSREF period is E*SYSREF_MULP. For out-of-range duty cycle setting, the SYSREF generation block should automatically infer 50:50 duty cycle.
Refer to the SYSREF Generator section for more information about the SYSREF period. |
| Select board |
- None
- Intel Agilex® 7 I-Series Transceiver-SoC Development Kit
|
Select the board for the design example.
- None—This option excludes hardware aspects for the design example. All the pin assignments will be set to virtual pins.
- Intel Agilex® 7 I-Series Transceiver-SoC Development Kit—This option automatically selects the project’s target device to match the device on this development kit. You may change the target device with the Change Target Device parameter below if your board revision has a different grade of the default targeted device.
|
| Test Pattern |
- PRBS-7
- PRBS-9
- PRBS-15
- PRBS-23
- Ramp
|
Select pattern generator and checker test pattern.
- Pattern Generator—JESD204C support PRBS pattern generator per data sample. This means that the width of the data is N+CS option. PRBS pattern generator and checker are useful for creating data sample stimulus for testing and it is not compatible with PRBS test mode on the ADC/DAC converter.
- Ramp Pattern Generator—JESD204C link layer operates normally but the transport later is disabled and the input from the formatter is ignored. Each lane transmits an identical octet stream that increments from 0x00 to 0xFF and then repeats. Ramp pattern test is enable by prbs_test_ctl.
- PRBS Pattern Checker—JESD204C PRBS scrambler is self synchronizing and it is expected that when the IP core is able to decode link up, the scrambling seed is already synchronized. PRBS scrambling seed will take up 8 octets to self initialize.
- Ramp Pattern Checker—JESD204C scrambling is self synchronizing and it is expected that when the IP core is able to decode link up, the scrambling seed is already synchronized. The first valid octet is loaded as the ramp initial value. Subsequent data must increment up to 0xFF and roll over to 0x00. Ramp pattern checker should check for identical pattern across all lanes.
|
| Enable Command Channel |
On, Off |
Select command channel pattern. |
| Clock Source Configuration |
- None
- 100 MHz OSC_CLK_1 pin
- 125 MHz OSC_CLK_1 pin
- 25 MHz OSC_CLK_1 pin
|
Select device initialization clock for the example design. Defaulted to the 125 MHz OSC_CLK_1 pin when the target devkit is selected. |