Security User Guide: Intel® FPGA Programmable Acceleration Card D5005

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ID 683877
Date 8/25/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Intel® FPGA PAC Security Features 3. Intel FPGA PAC Security Flow 4. Using fpgasupdate 5. Document Revision History for Security User Guide
1. Overview x
1.1. About This Document 1.2. Prerequisites 1.3. Related Documentation 1.4. Glossary
2. Intel® FPGA PAC Security Features x
2.1. Secure Image Updates 2.2. Anti-Rollback Capability 2.3. Key Management 2.4. Authentication 2.5. Encryption
3. Intel FPGA PAC Security Flow x
3.1. Installing PACSign 3.2. PACSign Tool 3.3. Creating Unsigned Images 3.4. Using an HSM Manager 3.5. Creating Keys 3.6. Root Entry Hash Bitstream Creation 3.7. Signing Images 3.8. Creating a CSK ID Cancellation Bitstream 3.9. PACSign PKCS11 Manager *.json Reference 3.10. Creating a Custom HSM Manager 3.11. PACSign Man Page
3.5. Creating Keys x
3.5.1. OpenSSL Key Creation 3.5.2. HSM Key Creation
3.7. Signing Images x
3.7.1. Signing OpenCL* Images
3.10. Creating a Custom HSM Manager x
3.10.1. HSM_MANAGER.get_public_key(public_key) 3.10.2. HSM_MANAGER.sign(data, key) 3.10.3. Signing Operation Flow
3.10.1. HSM_MANAGER.get_public_key(public_key) x
3.10.1.1. PUBLIC_KEY.get_X_Y() 3.10.1.2. PUBLIC_KEY.get_permission() 3.10.1.3. PUBLIC_KEY.get_ID() 3.10.1.4. PUBLIC_KEY.get_content_type()
4. Using fpgasupdate x
4.1. Troubleshooting
1. Overview
2. Intel® FPGA PAC Security Features
3. Intel FPGA PAC Security Flow
4. Using fpgasupdate
5. Document Revision History for Security User Guide

4. Using fpgasupdate

Use the fpgasupdate command to securely update the following files in flash:
  • BMC Nios® firmware and Intel® MAX® 10 FPGA images
  • FIM images
  • AFU (partial reconfiguration) images
When you call fpgasupdate the BMC orchestrates the update.
  • The BMC restricts all access to the flash until the fpgasupdate tool sends a request to the BMC to begin the update process.
  • The BMC rejects an update request if another update is currently in progress. The BMC monitors flash write and update counts and delays an update 30 seconds if more than 1,000 updates have occurred, and 60 seconds if more than 2,000 updates have occurred.
  • The BMC grants access only to a staging area in the flash, and only for enough time for the host to write an update into the staging area.
  • The BMC then restricts all flash write access to ensure the update image cannot be changed during or after the authentication process.
  • During the fpgasupdate process, the Nios® in the BMC stops polling the sensors and updating the platform level data model (PLDM) registers but responds to PLDM requests. Thus, any PLDM reads or fpgad polling during fpgasupdate returns stale data from before the update began.
  • If authentication is successful, the BMC copies the image from the staging area into the appropriate section in flash.
To use the command type: 
$ sudo fpgasupdate [--log-level=<level>] file [bdf]
where the following options are as follows:
Table 6.  fpgasupdate Options
Parameters Options Notes
level state, ioctl, debug, info, warning, error, critical. Default value is state. N/A
file The secure update file that you program in the Intel® FPGA PAC N/A
[bdf]
Note: You must provide the BDF assigned to the PCIe* DevID 0b30 on your system.
[ssss:]bb:dd:f, corresponding to PCIe segment, bus, device, function. The segment is optional; if omitted, a segment of 0000 is assumed. If there is only one Intel® FPGA PAC in the system, then bdf may be omitted. In this case, fpgasupdate determines the address automatically.

Section Content
Troubleshooting

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