AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

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ID 683875
Date 1/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Tutorial Overview 2. Tutorial Walkthrough 3. Tutorial Results 4. Document Revision History for AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design
1. Tutorial Overview x
1.1. PR Debug Considerations 1.2. Tutorial Software and Hardware Requirements 1.3. Tutorial Design Description 1.4. Downloading the Tutorial Design
1.4. Downloading the Tutorial Design x
1.4.1. Tutorial Design Files
2. Tutorial Walkthrough x
2.1. Step 1: Getting Started 2.2. Step 2: Preparing the Base Revision 2.3. Step 3: Preparing the Implementation Revisions for Debugging 2.4. Step 4: Configuring Signal Tap Logic Analyzer 2.5. Step 5: Generating Programming Files 2.6. Step 6: Programming the FPGA Device 2.7. Step 7: Performing Data Acquisition
2.2. Step 2: Preparing the Base Revision x
2.2.1. Preparing the Static Region 2.2.2. Preparing the Default PR Persona
2.4. Step 4: Configuring Signal Tap Logic Analyzer x
2.4.1. Tapping Signals in the Implementation Persona 2.4.2. Configuring Data Acquisition 2.4.3. Setting Trigger Conditions
2.4.2. Configuring Data Acquisition x
2.4.2.1. Add Acquisition Clock 2.4.2.2. Add Storage Parameters
3. Tutorial Results x
3.1. Waveforms for Slow Implementation 3.2. Waveforms for Default Implementation 3.3. Waveforms for Empty Implementation
1. Tutorial Overview
2. Tutorial Walkthrough
3. Tutorial Results
4. Document Revision History for AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

1.4.1. Tutorial Design Files

The design folder contains two subfolders: The start folder contains the files that you need to follow this tutorial, and the finish folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.

Table 1.  Description of Tutorial Design Files in start Folder
File Name Description
top.sv

Top-level file.

Contains the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module.

This module also instantiates the SLD JTAG Bridge Agent for debugging purposes.
top_counter.sv Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and powers LED[2] and LED[3] via the blinking_led module.
blinking_led.sdc Defines the timing constraints for the project.
blinking_led.sv This module acts as the PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3].This module also instantiates the SLD JTAG Bridge Host and the Intel Configuration Reset Release Endpoint to Debug Logic IP for debugging the default persona.
blinking_led.qpf Intel® Quartus® Prime project file that contains a list of all the revisions in the project.
blinking_led.qsf Intel® Quartus® Prime settings file that contains assignments and settings for the base revision of the project.
blinking_led_default.qsf Contains assignments and settings for the blinking_led_default implementation revision of the project.
blinking_led_slow.qsf Contains assignments and settings for the blinking_led_slow implementation revision of the project.
blinking_led_empty.qsf Contains assignments and settings for the blinking led empty of the project.
blinking_led_slow.sv Slower version of the PR logic. On this version, the led blinks at a slower rate than the default PR persona.

The module receives the registered output of top_counter module, which controls LED[2]and LED[3]. This module also instantiates the SLD JTAG Bridge Host and the Intel Configuration Reset Release Endpoint to Debug Logic IP for debugging this persona.

blinking_led_empty.sv Empty version of the PR logic. This module holds the outputs at a constant.

The module receives the registered output of top_counter module, which controls LED[2] and LED[3]. This module also instantiates the SLD JTAG Bridge Host and the Intel Configuration Reset Release Endpoint to Debug Logic IP for debugging this persona.

The following Figure shows the list of files in the finish folder:

Figure 3. Tutorial Design Files in finish Folder
Level Two Title