AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

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ID 683875
Date 1/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Tutorial Overview 2. Tutorial Walkthrough 3. Tutorial Results 4. Document Revision History for AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design
1. Tutorial Overview x
1.1. PR Debug Considerations 1.2. Tutorial Software and Hardware Requirements 1.3. Tutorial Design Description 1.4. Downloading the Tutorial Design
1.4. Downloading the Tutorial Design x
1.4.1. Tutorial Design Files
2. Tutorial Walkthrough x
2.1. Step 1: Getting Started 2.2. Step 2: Preparing the Base Revision 2.3. Step 3: Preparing the Implementation Revisions for Debugging 2.4. Step 4: Configuring Signal Tap Logic Analyzer 2.5. Step 5: Generating Programming Files 2.6. Step 6: Programming the FPGA Device 2.7. Step 7: Performing Data Acquisition
2.2. Step 2: Preparing the Base Revision x
2.2.1. Preparing the Static Region 2.2.2. Preparing the Default PR Persona
2.4. Step 4: Configuring Signal Tap Logic Analyzer x
2.4.1. Tapping Signals in the Implementation Persona 2.4.2. Configuring Data Acquisition 2.4.3. Setting Trigger Conditions
2.4.2. Configuring Data Acquisition x
2.4.2.1. Add Acquisition Clock 2.4.2.2. Add Storage Parameters
3. Tutorial Results x
3.1. Waveforms for Slow Implementation 3.2. Waveforms for Default Implementation 3.3. Waveforms for Empty Implementation
1. Tutorial Overview
2. Tutorial Walkthrough
3. Tutorial Results
4. Document Revision History for AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

2.2.1. Preparing the Static Region

  1. Ensure that blinking_led is the current revision.

    To change the revision to the blinking_led revision, click Project > Revisions and set blinking_led as the current revision.

  2. Add the SLD JTAG Bridge Agent Intel® FPGA IP to the design:
    1. In the IP Catalog (Tools > IP Catalog), type SLD JTAG Bridge Agent, and double-click the SLD JTAG Bridge Agent Intel® FPGA IP .
    2. In the New IP Variant dialog box, type sld_agent as the file name, and then click Create.
      Figure 4. New IP Variant Dialog Box
    3. In the parameter editor, use the default parameterization for sld_agent. Click Generate HDL and then click Generate.

      Save your changes, if prompted.

      Figure 5. SLD JTAG Bridge Agent Intel® FPGA IP Parameters
      The parameter editor generates the sld_agent.ip IP variation file and adds the file to the blinking_led project.
    4. Close the parameter editor.
    5. Verify whether the sld_agent IP variant appears in the IP Components tab of the Project Navigator.
      Figure 6. sld_agent IP Variant in Project Navigator
      If the IP variant does not appear in the Project Navigator, click Project > Add/Remove Files in Project, find the sld_agent.ip file, and add to the project.
    6. In the top.sv file, instantiate the sld_agent IP in the base revision by uncommenting the following block of code: 
      //==============
//Uncomment this block to enable Signal Tap

wire tck;
wire tms;
wire tdi;
wire vir_tdi;
wire ena;
wire tdo;
		
sld_agent u_sld_agent (
 .tck  (tck),  //  output,  width = 1, connect_to_bridge_host.tck
 .tms  (tms),  //  output,  width = 1, .tms
 .tdi  (tdi),  //  output,  width = 1, .tdi
 .vir_tdi (vir_tdi), //  output,  width = 1, .vir_tdi
 .ena  (ena),  //  output,  width = 1,  .ena
 .tdo  (tdo)   //  input,   width = 1,  .tdo
);

//==============
  3. Add the Reset Release Intel FPGA IP to the design:
    1. In the IP Catalog (Tools > IP Catalog), type Reset Release, and double-click the Reset Release Intel FPGA IP.
    2. In the New IP Variant dialog box, type reset_release as the file name, and then click Create.
      Figure 7. New IP Variant Dialog Box
    3. In the parameter editor, under Type of reset output port, select Conduit Interface. Click Generate HDL and then click Generate.

      Save your changes, if prompted.

      Figure 8. Reset Release Intel FPGA IP Parameters
      The parameter editor generates the reset_release.ip IP variation file and adds the file to the blinking_led project.
    4. Close the parameter editor.
    5. Verify whether the reset_release IP variant appears in the IP Components tab of the Project Navigator.
      Figure 9. reset_release IP Variant in Project Navigator
      If the IP variant does not appear in the Project Navigator, click Project > Add/Remove Files in Project, find the reset.ip file, and add it to the project.
    6. In the blinking_led.sv file, instantiate the reset_release IP in the default persona by uncommenting the following block of code: 
      //==============
//Uncomment this block to enable Signal Tap

wire connect_to_conf_rst;

reset_release u_reset_release (ninit_done (connect_to_conf_rst)  //  output,  width = 1, ninit_done.ninit_done
 );

//==============
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