1. AN 922: Using the ECO Compilation Flow
In a typical FPGA project development cycle, the specification of the programmable logic portion of the design can change during the design process. The Intel® Quartus® Prime software supports these last-minute, targeted engineering change orders (ECOs), even after full compilation is complete. This application note demonstrates implementation of ECO's with an example design.
ECOs typically occur during the design verification stage. For example, during verification you may determine that the design requires a small change, such as a netlist connection change, correcting a LUT logic error, or placing a node in a new location. Implementing an ECO change, rather than changing RTL and fully recompiling the design, requires significantly less time, and changes only the affected logic.
You specify the ECO commands in a Tcl script using the ::quartus::eco package.
ECO Change | ECO Commands |
---|---|
Route | |
Tie-Off | |
Lutmask | |
Slew Rate | |
Current Strength | |
Delay Chains | |
Update MIF | |
IOPLL Ref Clock ( Intel® Stratix® 10 devices only) | |
Create New Node | |
Remove Node | |
Place Node | |
Unplace Node | |
Create Wirelut | |
The activities of this application note are divided into the following sections:
Note: The Intel® Quartus® Prime Pro Edition software supports ECOs only for Intel® Stratix® 10 and Intel® Agilex™ devices.