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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Stratix® 10 SoC FPGA Boot Flow
8. Stratix® 10 SoC FPGA Boot User Guide Archives
9. Document Revision History for Stratix® 10 SoC FPGA Boot User Guide
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
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7.1.1. HPS Reset Pin
You can configure this pin through Quartus® Prime Pro Edition.
Pin Function | Possible Settings | Functional Description |
---|---|---|
HPS cold nreset | SDM_IO0, SDM_IO10-16 | Assert this pin to trigger cold reset to the HPS. If the HPS is cold reset via software, this pin becomes an output pin and remain low until the HPS cold reset sequence is complete. |