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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow
8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives
9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
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3.1.1. Power-On Reset (POR)
Ensure you power each of the power rails according to the power sequencing consideration until they reach the required voltage levels. In addition, the power-up sequence must meet either the standard or the fast power-on reset (POR) delay time.