External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families
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11.1. DDR2 SDRAM LATENCY
The following table shows the DDR2 SDRAM latency in full-rate memory clock cycles.
Latency in Full-Rate Memory Clock Cycles |
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---|---|---|---|---|---|---|---|
Rate |
Controller Address & Command |
PHY Address & Command |
Memory Maximum Read |
PHY Read Return |
Controller Read Return |
Round Trip |
Round Trip Without Memory |
Half |
10 |
EWL: 3 |
3–7 |
6 |
4 |
EWL: 26–30 |
EWL: 23 |
OWL: 4 |
OWL: 27–31 |
OWL: 24 |
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Full |
5 |
0 |
3–7 |
4 |
10 |
22–26 |
19 |
Notes to Table:
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