1. Quick Start Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 24.3 |
| IP Version 4.0.0 |
The enhanced Common Public Radio Interface (eCPRI) Intel® FPGA IP implements the eCPRI specification version 2.0. The eCPRI Intel® FPGA IP provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design example in hardware.
The compiled hardware design example runs on:
- Agilex 5 FPGA E-Series 065B Premium Development Kit
- Agilex™ 7 I-Series FPGA Development Kit
- Agilex™ 7 I-Series Transceiver-SoC Development Kit
- Agilex™ 7 F-Series Transceiver-SoC Development Kit
- Stratix® 10 GX Transceiver Signal Integrity Development Kit for the H-tile design examples
- Stratix® 10 TX Transceiver Signal Integrity Development Kit for the E-tile design examples
- Arria® 10 GX Transceiver Signal Integrity Development Kit
The testbench and design example supports 25G and 10G data rates for Stratix® 10 H-tile or E-tile, Agilex™ 7 E-tile or F-tile, and Agilex 5 device variations of the eCPRI IP.
The eCPRI design example has the following lmitations:
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- The interworking function (IWF) is only available for 9.8 Gbps CPRI line bit rate.
- The design does not support dynamic reconfiguration for 10G data rate in Arria® 10 designs.
- In Agilex 5 devices, the design does not support IWF and multichannel configurations. The design supports 10G or 25G Ethernet data rate depending on the device selected. For more information, refer to GTS Ethernet Hard IP Design Example User Guide. The design does not support dynamic reconfiguration between 25G and 10G Ethernet data rates.
- The design does not support L2/L3 Parser off configuration.
The eCPRI Intel® FPGA IP design example supports the following features:
- Internal TX to RX serial loopback mode
- Traffic generator and checker
- Basic packet checking capabilities
- System Console to run the design and reset the design for retesting
Figure 1. Development Steps for the Design Example