eCPRI Intel® FPGA IP Design Example User Guide

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ID 683837
Date 12/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example 1.8. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. eCPRI IP Hardware Design Example 2.3. Simulation Design Example 2.4. eCPRI IP Design Example Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide

4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.12.01 24.3 4.0.0
  • Added support for 25G Ethernet data rate.
  • Changed Agilex 5 FPGA E-Series 065B Modular Development Kit to Agilex 5 FPGA E-Series 065B Premium Development Kit
2024.08.16 24.2 3.0.3 Added support for Agilex 5 devices:
  • Added simulation block diagram for Agilex 5 devices.
  • Added support for Agilex 5 FPGA E-Series 065B Modular Development Kit
  • Added hardware block diagram for Agilex 5 devices.
2024.05.18 24.1 3.0.2
  • Added support for Nios V processor.
  • Removed support for Nios II.
2023.05.19 23.1 2.0.3
  • Updated the Simulating the Design Example Testbench section in the Quick Start Guide chapter.
  • Updated the product family name to "Intel Agilex 7".
2022.11.15 22.3 2.0.1 Updated instructions for VCS* simulator in section: Simulating the Design Example Testbench.
2022.07.01 22.1 1.4.1
  • Added the hardware design example support for Agilex™ 7 F-tile device variations.
  • Added support for the following development kits:
    • Agilex™ 7 I-Series FPGA Development Kit
    • Agilex™ 7 I-Series Transceiver-SoC Development Kit
  • Added support for QuestaSim* simulator.
  • Removed support for ModelSim* SE simulator.
2021.10.01 21.2 1.3.1
  • Added support for the Agilex™ 7 F-tile devices.
  • Added support for multi-channel designs.
  • Updated Table: eCPRI Intel FPGA IP Hardware Design Example Register Map.
  • Removed support for NCSim simulator.
2021.02.26 20.4 1.3.0
  • Added support for the Agilex™ 7 E-tile devices.
2021.01.08 20.3 1.2.0
  • Changed the document title from eCPRI Intel Stratix 10 FPGA IP Design Example User Guide to eCPRI Intel FPGA IP Design Example User Guide.
  • Added support for Arria® 10 designs.
  • The eCPRI IP design example is now available with interworking function (IWF) feature support.
  • Added a note to clarify that eCPRI design example with IWF feature is only available for 9.8 Gbps CPRI line bit rate.
  • Added conditions in section Generating the Design when generating the design example with Interworking Function (IWF) Support parameter enabled.
  • Added sample simulation test run output with IWF feature enabled in section Simulating the Design Example Testbench.
  • Added new section Enabling Dynamic Reconfiguration to the Ethernet IP.
  • Updated hardware test sample output in section Testing the eCPRI Intel FPGA IP Design Example.
  • Updated the Figure: eCPRI Intel FPGA IP Hardware Design Examples High Level Block Diagram to include IWF Type 0, CPRI MAC, and CPRI PHY blocks.
  • Updated Table: Design Example Interface Signals to include Arria® 10 device and IWF related signals.
  • Updated Table: eCPRI Intel FPGA IP Hardware Design Example Register Map.
2020.06.15 20.1 1.1.0
  • Added support for 10G data rate.
  • flow.c file is now available with design example generation to select loopback mode.
  • Modified the sample output for simulation test run in section Simulating the Design Example Testbench.
  • Added frequency value for running 10G data rate design in section Compiling and Configuring the Design Example in Hardware.
  • Made following changes in section Testing the eCPRI Intel FPGA IP Design Example:
    • Added commands to switch data rate between 10G and 25G
    • Added sample output for data rate switching
    • Added TEST_MODE variable information to select loopback in E-tile device variations.
  • Modified eCPRI Intel FPGA IP Hardware Design Examples High Level Block Diagram to include new blocks.
  • Updated Table: Design Example Interface Signals to include new signal.
  • Updated Design Example Register Map section.
  • Added new appendix section:Generating and Downloading the Executable and Linking Format (.elf) Programming File .
2020.04.13 19.4 1.0.0 Initial release.
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