eCPRI Intel® FPGA IP Design Example User Guide

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ID 683837
Date 5/19/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide A. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. Hardware Design Example 2.3. Simulation Design Example 2.4. Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide
A. Generating and Downloading the Executable and Linking Format (.elf) Programming File

1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP

By default, the dynamic reconfiguration is disabled in the eCPRI IP design example and it's only applicable to Intel® Stratix® 10 (E-tile and H-tile) and Intel® Agilex™ 7 (E-tile) design examples.
  1. Look for the following line in the test_wrapper.sv from the generated <design_example_dir>/simulation/testbench directory:

    parameter ETHERNET_DR_EN = 0

  2. Change the value from 0 to 1:

    parameter ETHERNET_DR_EN = 1

  3. Rerun the simulation using the same generated example design directory.
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