eCPRI Intel® FPGA IP Design Example User Guide

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ID 683837
Date 5/19/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide A. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. Hardware Design Example 2.3. Simulation Design Example 2.4. Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide
A. Generating and Downloading the Executable and Linking Format (.elf) Programming File

1.6. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel® device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_dir>/synthesis/quartus/ecpri_ed.qpf.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in <design_example_dir>/synthesis/quartus/output_files directory. Follow these steps to program the hardware design example on the Intel® FPGA device:
    1. Connect Development Kit to the host computer.
    2. Launch the Clock Control application, which is part of the development kit, and set the new frequencies for the design example. Below is the frequency setting in the Clock Control application:
      • If you are targeting your design on Intel® Stratix® 10 GX SI Development Kit:
        • U5, OUT8- 100 MHz
        • U6, OUT3- 322.265625 MHz
        • U6, OUT4 and OUT5- 307.2 MHz
      • If you are targeting your design on Intel® Stratix® 10 TX SI Development Kit:
        • U1, CLK4- 322.265625 MHz (For 25G data rate)
        • U6- 156.25 MHz (For 10G data rate)
        • U3, OUT3- 100 MHz
        • U3, OUT8- 153.6 MHz
      • If you are targeting your design on Intel® Agilex™ 7 F-Series Transceiver-SoC Development Kit:
        • U37, CLK1A- 100 MHz
        • U34, CLK0P- 156.25 MHz
        • U38, OUT2_P- 153.6 MHz
      • If you are targeting your design on Intel® Arria® 10 GX SI Development Kit:
        • U52, CLK0- 156.25 MHz
        • U52, CLK1- 250 MHz
        • U52, CLK3- 125 MHz
        • Y5- 307.2 MHz
        • Y6- 322.265625 MHz
    3. On the Tools menu, click Programmer.
    4. In the Programmer, click Hardware Setup.
    5. Select a programming device.
    6. Select and add the Development Kit to which your Intel® Quartus® Prime Pro Edition session can connect.
    7. Ensure that Mode is set to JTAG.
    8. Select the device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    9. Load the .sof file to your respective Intel® FPGA device.
    10. Load the Executable and Linking format (.elf) file to your Intel® Stratix® 10 or Intel® Agilex™ 7 device if you plan to perform the dynamic reconfiguration (DR) to switch the data rate between 25G and 10G. Follow the instructions from the Generating and Downloading the Executable and Linking Format (.elf) Programming File to generate the .elf file.
    11. In the row with your .sof, check the Program/Configure box for the .sof file.
    12. Click Start.
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