Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 10/23/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Creating a Partial Reconfiguration Design 2. Partial Reconfiguration Solutions IP User Guide A. Quartus® Prime Pro Edition User Guides
1. Creating a Partial Reconfiguration Design x
1.1. What's New In This Version 1.2. Partial Reconfiguration Terminology 1.3. Partial Reconfiguration Process Sequence 1.4. Internal Host Partial Reconfiguration 1.5. External Host Partial Reconfiguration 1.6. Partial Reconfiguration Design Flow 1.7. Partial Reconfiguration Design Considerations 1.8. Hierarchical Partial Reconfiguration 1.9. Partial Reconfiguration Design Timing Analysis 1.10. Partial Reconfiguration Design Simulation 1.11. Partial Reconfiguration Design Debugging 1.12. Partial Reconfiguration Security ( Stratix® 10 Designs) 1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs) 1.14. Avoiding PR Programming Errors 1.15. Exporting a Version-Compatible Compilation Database for PR Designs 1.16. Creating a Partial Reconfiguration Design Revision History
1.6. Partial Reconfiguration Design Flow x
1.6.1. Step 1: Identify Partial Reconfiguration Resources 1.6.2. Step 2: Create Design Partitions 1.6.3. Step 3: Floorplan the Design 1.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP 1.6.5. Step 5: Define Personas 1.6.6. Step 6: Create Revisions for Personas 1.6.7. Step 7: Compile the Base Revision and Export the Static Region 1.6.8. Step 8: Setup PR Implementation Revisions 1.6.9. Step 9: Program the FPGA Device
1.6.3. Step 3: Floorplan the Design x
1.6.3.1. Applying Floorplan Constraints Incrementally
1.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP x
1.6.4.1. Adding the Partial Reconfiguration Controller Intel FPGA IP 1.6.4.2. Adding the Partial Reconfiguration Controller Arria® 10/Cyclone 10 FPGA IP
1.6.7. Step 7: Compile the Base Revision and Export the Static Region x
1.6.7.1. Understanding PR Logic Utilization Reports
1.6.9. Step 9: Program the FPGA Device x
1.6.9.1. Generating PR Bitstream Files 1.6.9.2. Generating PR Bitstream Files 1.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking 1.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples 1.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Arria® 10 and Cyclone® 10 GX Designs)
1.7. Partial Reconfiguration Design Considerations x
1.7.1. Partial Reconfiguration Design Guidelines 1.7.2. PR Design Timing Closure Best Practices 1.7.3. PR File Management 1.7.4. Evaluating PR Region Initial Conditions 1.7.5. Creating Wrapper Logic for PR Regions 1.7.6. Creating Freeze Logic for PR Regions 1.7.7. Resetting the PR Region Registers 1.7.8. Promoting Global Signals in a PR Region 1.7.9. Planning Clocks and other Global Routing 1.7.10. Implementing Clock Enable for On-Chip Memories
1.7.3. PR File Management x
1.7.3.1. Method 1 (Preferred): Specify Unique Entity and File Names for Each Persona 1.7.3.2. Method 2: Set QSF Assignment for a Parameterized PR Persona
1.7.8. Promoting Global Signals in a PR Region x
1.7.8.1. Viewing Row Clock Region Boundaries
1.7.10. Implementing Clock Enable for On-Chip Memories x
1.7.10.1. Clock Gating
1.8. Hierarchical Partial Reconfiguration x
1.8.1. Using Parent QDB Files from Different Compiles
1.9. Partial Reconfiguration Design Timing Analysis x
1.9.1. Running Timing Analysis on Aggregate Revisions
1.10. Partial Reconfiguration Design Simulation x
1.10.1. Partial Reconfiguration Simulation Flow 1.10.2. Simulating PR Persona Replacement
1.10.2. Simulating PR Persona Replacement x
1.10.2.1. altera_pr_persona_if Module 1.10.2.2. altera_pr_wrapper_mux_out Module 1.10.2.3. altera_pr_wrapper_mux_in Module
1.11. Partial Reconfiguration Design Debugging x
1.11.1. Debugging PR Designs with the Signal Tap Logic Analyzer 1.11.2. Instantiating the Intel Configuration Reset Release Endpoint to Debug Logic IP
1.12. Partial Reconfiguration Security ( Stratix® 10 Designs) x
1.12.1. PR Bitstream Security Validation ( Stratix® 10 Designs) 1.12.2. PR Bitstream Authentication ( Stratix® 10 Designs) 1.12.3. PR Bitstream Encryption ( Stratix® 10 Designs)
1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs) x
1.13.1. Generating an Encrypted PR Bitstream ( Arria® 10 or Cyclone® 10 GX Designs) 1.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Arria® 10 or Cyclone® 10 GX Designs) 1.13.3. Data Compression Comparison
1.15. Exporting a Version-Compatible Compilation Database for PR Designs x
1.15.1. Version-Compatible Database Flow for PR Designs 1.15.2. Generating a Version-Compatible Compilation Database for PR Designs
2. Partial Reconfiguration Solutions IP User Guide x
2.1. Internal and External PR Host Configurations 2.2. Partial Reconfiguration Controller Intel FPGA IP 2.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP 2.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP 2.5. Partial Reconfiguration Region Controller Intel® FPGA IP 2.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP 2.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP 2.8. Generating and Simulating Intel® FPGA IP 2.9. Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive 2.10. Partial Reconfiguration Solutions IP User Guide Revision History
2.2. Partial Reconfiguration Controller Intel FPGA IP x
2.2.1. Memory Map 2.2.2. Parameters 2.2.3. Ports 2.2.4. Timing Specifications 2.2.5. PR Error Recovery 2.2.6. Secure Device Manager Firmware Error Reporting
2.2.5. PR Error Recovery x
2.2.5.1. PR Error Recovery Timing Specifications
2.2.6. Secure Device Manager Firmware Error Reporting x
2.2.6.1. SDM Firmware Error Reporting Timing Specification
2.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP x
2.3.1. Agent Interface 2.3.2. Reconfiguration Sequence 2.3.3. Interrupt Interface 2.3.4. Parameters 2.3.5. Ports 2.3.6. Timing Specifications 2.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation 2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation 2.3.9. PR Control Block Signals 2.3.10. Configuring an External Host for Arria® 10 or Cyclone® 10 GX Designs
2.3.4. Parameters x
2.3.4.1. Error Detection CRC Requirements
2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation x
2.3.8.1. PR Control Block and CRC Block VHDL Component Declaration
2.3.9. PR Control Block Signals x
2.3.9.1. PR Control Block Signal Timing Diagrams
2.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP x
2.4.1. Parameters 2.4.2. Ports 2.4.3. Partial Reconfiguration External Controller Intel FPGA IP Timing Specifications 2.4.4. Configuring an External Host for Agilex® 7, Agilex™ 5, and Stratix® 10 Designs
2.5. Partial Reconfiguration Region Controller Intel® FPGA IP x
2.5.1. Registers 2.5.2. Parameters 2.5.3. Ports
2.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP x
2.6.1. Parameters 2.6.2. Interface Ports
2.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP x
2.7.1. Parameters 2.7.2. Ports
2.8. Generating and Simulating Intel® FPGA IP x
2.8.1. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.8.2. Running the Freeze Bridge Update script 2.8.3. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.8.4. Arria® 10 and Cyclone® 10 GX PR Control Block Simulation Model 2.8.5. Generating the PR Persona Simulation Model 2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model x
2.8.6.1. Monitoring the SDM 2.8.6.2. Simulating Unknown Outputs and Persona Activation 2.8.6.3. Simulation RBF Required Word Sequence
Answers to Top FAQs
1. Creating a Partial Reconfiguration Design
2. Partial Reconfiguration Solutions IP User Guide
A. Quartus® Prime Pro Edition User Guides

2.2.6.1. SDM Firmware Error Reporting Timing Specification

Timing Diagram: PR Operation with SDM Firmware Error Reporting Signals - PR Controller Intel FPGA IP (Avalon Streaming) shows the timing diagram of PR operation with the SDM firmware error reporting signal usage in Avalon-ST mode of the PR Controller IP. During PR operation, you can read the pr_fw_handshake and pr_fw_response signals after a PR error to learn more about the error. For example, once you detect the PR operation has ended with the status[2:0], you can continue by reading the pr_fw_handshake and pr_fw_response signals.

In this example, the PR operation ends with PR_ERROR, as indicated by the status[2:0] = 3’b100. For error details, you can read the pr_fw_handshake to determine in which stage the PR operation fails. You can read pr_fw_response to determine the error code that the SDM returns.

Figure 54. Timing Diagram: PR Operation with SDM Firmware Error Reporting Signals - PR Controller Intel FPGA IP (Avalon Streaming)

The following steps correspond to the sequence in the timing diagram:

  1. Assert pr_start to begin the PR operation.
  2. Stream the PR bitstream on avst_sink_ready and avst_sink_valid ports.
  3. The SDM detects a PR_ERROR causing avst_sink_ready to be de-asserted to backpressure incoming PR bitstream.
  4. You detect that status[2:0] is updated to 0x4 (3’b100) to indicate that ‘PR_ERROR is triggered’. From this status information, you can determine that an error occurred during the PR operation.
  5. To learn more about the PR operation failure, read the pr_fw_handshake[7:0] and pr_fw_response[31:0] signals to determine the error code and PR stage of the failure.

Timing Diagram: PR Operation with SDM Firmware Error Reporting Signals - PR Controller Intel FPGA IP (Avalon Memory-Mapped) shows the PR operation timing diagram with the SDM firmware error reporting signal usage in Avalon memory-mapped mode of the PR Controller Intel FPGA IP. During a PR operation, you can read the CSR registers (0x3 for PR_FW_HANDSHAKE, and 0x4 for PR_FW_RESPONSE) after a PR error to learn more about the error. For example, once you detect that the PR operation ends with an error by IRQ assertion, and after reading CSR register 0x1 (PR_CSR) that holds the PR status[2:0] value, you can continue by reading the CSR registers 0x3 and 0x4, as .

Figure 55. Timing Diagram: PR Operation with SDM Firmware Error Reporting Signals - PR Controller Intel FPGA IP (Avalon Memory-Mapped)

The following steps correspond to the sequence in the timing diagram:

  1. Start the PR operation by writing to CSR address 0x1 (PR_CSR) with 0x21.This action enables the use of the irq signal and sets the pr_start to begin the PR operation. After 1 clock cycle, status[2:0] updates to 0x2 (3’b010) to indicate ‘PR operation is in progress'.
  2. Read the CSR address 0x1 (PR_CSR) to obtain the status[2:0] of the PR operation. The value read back is 0x24, which translates to status[2:0] = 3’b010, indicating 'PR operation is in progress'.
  3. Start writing the PR bitstream in CSR address 0x0 (PR_DATA).
  4. You read PR_CSR and observe that irq was asserted and that PR_ERROR is the status.

The pr_fw_handshake register holds the current location of the mailbox handshake between the PR IP and the SDM. If the PR IP is interrupted during PR, the pr_fw_handshake register indicates the last position of the mailbox handshake. The pr_fw_handshake register also enables you to associate the value held in pr_fw_response to a specific mailbox command.

Table 17.  pr_fw_handshake Register Values
Register Value Description
0 The PR IP has not yet sent any mailbox command to the SDM to initiate the partial reconfiguration operation.
1 The PR IP has sent the mailbox command to the SDM to initiate the partial reconfiguration operation and is awaiting a response.
2 PR IP has received the mailbox response from the SDM on the partial reconfiguration operation initiation.
3 The PR IP has sent the mailbox command to the SDM to query the last partial reconfiguration status and is awaiting a response.
4 The PR IP has received the mailbox response from the SDM on the last partial reconfiguration status.
5 The PR IP has sent the mailbox command to the SDM to initiate the partial reconfiguration operation from the data source selected by MSEL and is awaiting a response.
6 The PR IP has received the mailbox response from the SDM on the partial reconfiguration operation from the data source selected by MSEL.
7 Reserved.
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