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1.1. What's New In This Version
1.2. Partial Reconfiguration Terminology
1.3. Partial Reconfiguration Process Sequence
1.4. Internal Host Partial Reconfiguration
1.5. External Host Partial Reconfiguration
1.6. Partial Reconfiguration Design Flow
1.7. Partial Reconfiguration Design Considerations
1.8. Hierarchical Partial Reconfiguration
1.9. Partial Reconfiguration Design Timing Analysis
1.10. Partial Reconfiguration Design Simulation
1.11. Partial Reconfiguration Design Debugging
1.12. Partial Reconfiguration Security ( Stratix® 10 Designs)
1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs)
1.14. Avoiding PR Programming Errors
1.15. Exporting a Version-Compatible Compilation Database for PR Designs
1.16. Creating a Partial Reconfiguration Design Revision History
1.6.1. Step 1: Identify Partial Reconfiguration Resources
1.6.2. Step 2: Create Design Partitions
1.6.3. Step 3: Floorplan the Design
1.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP
1.6.5. Step 5: Define Personas
1.6.6. Step 6: Create Revisions for Personas
1.6.7. Step 7: Compile the Base Revision and Export the Static Region
1.6.8. Step 8: Setup PR Implementation Revisions
1.6.9. Step 9: Program the FPGA Device
1.6.9.1. Generating PR Bitstream Files
1.6.9.2. Generating PR Bitstream Files
1.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking
1.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples
1.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Arria® 10 and Cyclone® 10 GX Designs)
1.7.1. Partial Reconfiguration Design Guidelines
1.7.2. PR Design Timing Closure Best Practices
1.7.3. PR File Management
1.7.4. Evaluating PR Region Initial Conditions
1.7.5. Creating Wrapper Logic for PR Regions
1.7.6. Creating Freeze Logic for PR Regions
1.7.7. Resetting the PR Region Registers
1.7.8. Promoting Global Signals in a PR Region
1.7.9. Planning Clocks and other Global Routing
1.7.10. Implementing Clock Enable for On-Chip Memories
2.1. Internal and External PR Host Configurations
2.2. Partial Reconfiguration Controller Intel FPGA IP
2.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP
2.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP
2.5. Partial Reconfiguration Region Controller Intel® FPGA IP
2.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP
2.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP
2.8. Generating and Simulating Intel® FPGA IP
2.9. Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive
2.10. Partial Reconfiguration Solutions IP User Guide Revision History
2.3.1. Agent Interface
2.3.2. Reconfiguration Sequence
2.3.3. Interrupt Interface
2.3.4. Parameters
2.3.5. Ports
2.3.6. Timing Specifications
2.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation
2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation
2.3.9. PR Control Block Signals
2.3.10. Configuring an External Host for Arria® 10 or Cyclone® 10 GX Designs
2.8.1. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
2.8.2. Running the Freeze Bridge Update script
2.8.3. IP Core Generation Output ( Quartus® Prime Pro Edition)
2.8.4. Arria® 10 and Cyclone® 10 GX PR Control Block Simulation Model
2.8.5. Generating the PR Persona Simulation Model
2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
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2.8.1. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
You configure Intel® FPGA IP in the Quartus® Prime parameter editor. Double-click any component in the IP Catalog to launch the parameter editor. The parameter editor allows you to define a custom variation of the IP. The parameter editor generates the IP variation synthesis and optional simulation files, and adds the .ip file representing the variation to your project automatically.
To locate, instantiate, and customize an IP in the parameter editor:
- Create or open an Quartus® Prime project (.qpf) to contain the instantiated IP variation.
- In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP to customize. To locate a specific component, type some or all of the component’s name in the IP Catalog search box. The New IP Variation window appears.
- Specify a top-level name for your custom IP variation. Do not include spaces in IP variation names or paths. The parameter editor saves the IP variation settings in a file named <your_ip> .ip. Click OK. The parameter editor appears.
Figure 84. IP Parameter Editor ( Quartus® Prime Pro Edition)
- Set the parameter values in the parameter editor and view the block diagram for the component. The Parameterization Messages tab at the bottom displays any errors in IP parameters:
- Optionally, select preset parameter values if provided for your IP. Presets specify initial parameter values for specific applications.
- Specify parameters defining the IP functionality, port configurations, and device-specific features.
- Specify options for processing the IP files in other EDA tools.
Note: Refer to your IP user guide for information about specific IP parameters. - Click Generate HDL. The Generation dialog box appears.
- Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
- To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
- To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
- Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
- After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.
Note: Some IPs generate different HDL implementations according to the IP parameters. The underlying RTL of these IP contains a unique hash code that prevents module name collisions between different variations of the IP. This unique code remains consistent, given the same IP settings and software version during IP generation. This unique code can change if you edit the IP's parameters or upgrade the IP version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script.
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