Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 10/23/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Creating a Partial Reconfiguration Design 2. Partial Reconfiguration Solutions IP User Guide A. Quartus® Prime Pro Edition User Guides
1. Creating a Partial Reconfiguration Design x
1.1. What's New In This Version 1.2. Partial Reconfiguration Terminology 1.3. Partial Reconfiguration Process Sequence 1.4. Internal Host Partial Reconfiguration 1.5. External Host Partial Reconfiguration 1.6. Partial Reconfiguration Design Flow 1.7. Partial Reconfiguration Design Considerations 1.8. Hierarchical Partial Reconfiguration 1.9. Partial Reconfiguration Design Timing Analysis 1.10. Partial Reconfiguration Design Simulation 1.11. Partial Reconfiguration Design Debugging 1.12. Partial Reconfiguration Security ( Stratix® 10 Designs) 1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs) 1.14. Avoiding PR Programming Errors 1.15. Exporting a Version-Compatible Compilation Database for PR Designs 1.16. Creating a Partial Reconfiguration Design Revision History
1.6. Partial Reconfiguration Design Flow x
1.6.1. Step 1: Identify Partial Reconfiguration Resources 1.6.2. Step 2: Create Design Partitions 1.6.3. Step 3: Floorplan the Design 1.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP 1.6.5. Step 5: Define Personas 1.6.6. Step 6: Create Revisions for Personas 1.6.7. Step 7: Compile the Base Revision and Export the Static Region 1.6.8. Step 8: Setup PR Implementation Revisions 1.6.9. Step 9: Program the FPGA Device
1.6.3. Step 3: Floorplan the Design x
1.6.3.1. Applying Floorplan Constraints Incrementally
1.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP x
1.6.4.1. Adding the Partial Reconfiguration Controller Intel FPGA IP 1.6.4.2. Adding the Partial Reconfiguration Controller Arria® 10/Cyclone 10 FPGA IP
1.6.7. Step 7: Compile the Base Revision and Export the Static Region x
1.6.7.1. Understanding PR Logic Utilization Reports
1.6.9. Step 9: Program the FPGA Device x
1.6.9.1. Generating PR Bitstream Files 1.6.9.2. Generating PR Bitstream Files 1.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking 1.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples 1.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Arria® 10 and Cyclone® 10 GX Designs)
1.7. Partial Reconfiguration Design Considerations x
1.7.1. Partial Reconfiguration Design Guidelines 1.7.2. PR Design Timing Closure Best Practices 1.7.3. PR File Management 1.7.4. Evaluating PR Region Initial Conditions 1.7.5. Creating Wrapper Logic for PR Regions 1.7.6. Creating Freeze Logic for PR Regions 1.7.7. Resetting the PR Region Registers 1.7.8. Promoting Global Signals in a PR Region 1.7.9. Planning Clocks and other Global Routing 1.7.10. Implementing Clock Enable for On-Chip Memories
1.7.3. PR File Management x
1.7.3.1. Method 1 (Preferred): Specify Unique Entity and File Names for Each Persona 1.7.3.2. Method 2: Set QSF Assignment for a Parameterized PR Persona
1.7.8. Promoting Global Signals in a PR Region x
1.7.8.1. Viewing Row Clock Region Boundaries
1.7.10. Implementing Clock Enable for On-Chip Memories x
1.7.10.1. Clock Gating
1.8. Hierarchical Partial Reconfiguration x
1.8.1. Using Parent QDB Files from Different Compiles
1.9. Partial Reconfiguration Design Timing Analysis x
1.9.1. Running Timing Analysis on Aggregate Revisions
1.10. Partial Reconfiguration Design Simulation x
1.10.1. Partial Reconfiguration Simulation Flow 1.10.2. Simulating PR Persona Replacement
1.10.2. Simulating PR Persona Replacement x
1.10.2.1. altera_pr_persona_if Module 1.10.2.2. altera_pr_wrapper_mux_out Module 1.10.2.3. altera_pr_wrapper_mux_in Module
1.11. Partial Reconfiguration Design Debugging x
1.11.1. Debugging PR Designs with the Signal Tap Logic Analyzer 1.11.2. Instantiating the Intel Configuration Reset Release Endpoint to Debug Logic IP
1.12. Partial Reconfiguration Security ( Stratix® 10 Designs) x
1.12.1. PR Bitstream Security Validation ( Stratix® 10 Designs) 1.12.2. PR Bitstream Authentication ( Stratix® 10 Designs) 1.12.3. PR Bitstream Encryption ( Stratix® 10 Designs)
1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs) x
1.13.1. Generating an Encrypted PR Bitstream ( Arria® 10 or Cyclone® 10 GX Designs) 1.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Arria® 10 or Cyclone® 10 GX Designs) 1.13.3. Data Compression Comparison
1.15. Exporting a Version-Compatible Compilation Database for PR Designs x
1.15.1. Version-Compatible Database Flow for PR Designs 1.15.2. Generating a Version-Compatible Compilation Database for PR Designs
2. Partial Reconfiguration Solutions IP User Guide x
2.1. Internal and External PR Host Configurations 2.2. Partial Reconfiguration Controller Intel FPGA IP 2.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP 2.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP 2.5. Partial Reconfiguration Region Controller Intel® FPGA IP 2.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP 2.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP 2.8. Generating and Simulating Intel® FPGA IP 2.9. Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive 2.10. Partial Reconfiguration Solutions IP User Guide Revision History
2.2. Partial Reconfiguration Controller Intel FPGA IP x
2.2.1. Memory Map 2.2.2. Parameters 2.2.3. Ports 2.2.4. Timing Specifications 2.2.5. PR Error Recovery 2.2.6. Secure Device Manager Firmware Error Reporting
2.2.5. PR Error Recovery x
2.2.5.1. PR Error Recovery Timing Specifications
2.2.6. Secure Device Manager Firmware Error Reporting x
2.2.6.1. SDM Firmware Error Reporting Timing Specification
2.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP x
2.3.1. Agent Interface 2.3.2. Reconfiguration Sequence 2.3.3. Interrupt Interface 2.3.4. Parameters 2.3.5. Ports 2.3.6. Timing Specifications 2.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation 2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation 2.3.9. PR Control Block Signals 2.3.10. Configuring an External Host for Arria® 10 or Cyclone® 10 GX Designs
2.3.4. Parameters x
2.3.4.1. Error Detection CRC Requirements
2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation x
2.3.8.1. PR Control Block and CRC Block VHDL Component Declaration
2.3.9. PR Control Block Signals x
2.3.9.1. PR Control Block Signal Timing Diagrams
2.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP x
2.4.1. Parameters 2.4.2. Ports 2.4.3. Partial Reconfiguration External Controller Intel FPGA IP Timing Specifications 2.4.4. Configuring an External Host for Agilex® 7, Agilex™ 5, and Stratix® 10 Designs
2.5. Partial Reconfiguration Region Controller Intel® FPGA IP x
2.5.1. Registers 2.5.2. Parameters 2.5.3. Ports
2.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP x
2.6.1. Parameters 2.6.2. Interface Ports
2.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP x
2.7.1. Parameters 2.7.2. Ports
2.8. Generating and Simulating Intel® FPGA IP x
2.8.1. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.8.2. Running the Freeze Bridge Update script 2.8.3. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.8.4. Arria® 10 and Cyclone® 10 GX PR Control Block Simulation Model 2.8.5. Generating the PR Persona Simulation Model 2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model x
2.8.6.1. Monitoring the SDM 2.8.6.2. Simulating Unknown Outputs and Persona Activation 2.8.6.3. Simulation RBF Required Word Sequence
Answers to Top FAQs
1. Creating a Partial Reconfiguration Design
2. Partial Reconfiguration Solutions IP User Guide
A. Quartus® Prime Pro Edition User Guides

2.3.5. Ports

The Partial Reconfiguration Controller Arria® 10 /Cyclone 10 FPGA IP includes the following interface ports.
Figure 58.  Partial Reconfiguration Controller Interface Ports (Internal Host)
Figure 59. Partial Reconfiguration Controller Interface Ports (External Host)
Table 24.  Clock/Reset Ports
Port Name Width Direction Function

nreset

1

Input

Asynchronous reset for the PR Controller IP core. Resetting the PR Controller IP core during a partial reconfiguration operation initiates the withdrawal sequence.

clk

1

Input

User input clock to the PR Controller IP core. The IP core has a maximum clock frequency of 100MHz.

The IP core ignores this signal during JTAG debug operations.

Table 25.  Freeze Interface Port
Port Name Width Direction Function

freeze

1

Output

Active high signal that freezes the PR interface signals of any region undergoing partial reconfiguration. De-assertion of this signal indicates the end of PR operation.

Use the Partial Reconfiguration Region Controller IP for this operation rather than the Partial Reconfiguration Controller IP freeze signal.

Table 26.  Conduit Interface PortsThese ports are available when Enable Avalon® Memory-Mapped agent interface is Off.
Port Name Width Direction Function

pr_start

1

Input

A 0 to 1 transition on this port initiates a PR event. You must assert this signal high for a minimum of one clock cycle, and de-assert the signal low prior to the end of the PR operation. This operation ensures the PR Controller IP core is ready to accept the next pr_start trigger event when the freeze signal is low.

The PR Controller IP core ignores this signal during JTAG debug operations.

data[]

1, 8, 16, or 32

Input

Selectable input PR data bus width, either x1, x8, x16, or x32.

Once a PR event triggers, the PR event is synchronous with the rising edge of the clk signal, whenever the data_valid signal is high, and the data_ready signal is high.

The PR Controller IP core ignores this signal during JTAG debug operations.

data_valid

1

Input

A 0 to 1 transition on this port indicates the data[] port contains valid data.

The PR Controller IP core ignores this signal during JTAG debug operations.

data_ready

1

Output

A 0 to 1 transition on this port indicates the PR Controller IP core is ready to read the valid data on the data[] port, whenever the data_valid signal asserts high. The data sender must stop sending valid data if this port is low.

This signal deasserts low during JTAG debug operations.

status[2:0]

1

Output

A 3-bit output that indicates the status of PR events. When the IP detects an error (PR_ERROR, CRC_ERROR, or incompatible bitstream error), this signal latches high. This signal only resets at the beginning of the next PR event, when pr_start is high, and freeze is low. For example:

3’b000 – power-up or nreset asserts

3’b001 – PR_ERROR triggers

3’b010 – CRC_ERROR triggers

3’b011 – Incompatible bitstream error detection

3’b100 – PR operation in progress

3’b101 – PR operation passes

3'b110 – Reserved bit

3'b111 – Reserved bit

Table 27.   Avalon® Memory-Mapped Slave Interface PortsThese signals are available when Enable Avalon® memory-mapped slave interface is On.
Port Name Width Direction Function

avmm_slave_address

4

Input

Avalon® memory-mapped address bus. The address bus is in the unit of Word addressing.

The PR Controller IP core ignores this signal during JTAG debug operations.

avmm_slave_read 1

Input

Avalon® memory-mapped read control.

The PR Controller IP core ignores this signal during JTAG debug operations.

avmm_slave_readdata 32

Output

Avalon® memory-mapped read data bus.

The PR Controller IP core ignores this signal during JTAG debug operations.

avmm_slave_write 1

Input

Avalon® memory-mapped write control.

The PR Controller IP core ignores this signal during JTAG debug operations.

avmm_slave_writedata 32

Input

Avalon® memory-mapped write data bus.

The PR Controller IP core ignores this signal during JTAG debug operations.

avmm_slave_waitrequest 1

Output

Indicates that the IP is busy. Also indicates that the IP core is unable to respond to a read or write request.

The IP core pulls this signal high during JTAG debug operations.
Table 28.  Interrupt Interface PortsThese ports are available when Enable interrupt interface is On.
Port Name Width Direction Function

irq

1

Output

The interrupt signal.
Table 29.  CRC BLOCK InterfaceThese ports are available when Use as Partial Reconfiguration Internal Host is Off, or when you instantiate the CRCBLOCK manually for an internal host.
Port Name Width Direction Function

crc_error_pin

1

Input

Available when you use the PR Controller IP core as an External Host. Connect this port to the dedicated CRC_ERROR pin of the FPGA undergoing partial reconfiguration.

Table 30.   PR Block InterfaceThese options are available when Use as Partial Reconfiguration Internal Host is Off, or when you instantiate the PRBLOCK manually for an internal host.
Port Name Width Direction Function

pr_ready_pin

1

Input

Connect this port to the dedicated PR_READY pin of the FPGA undergoing partial reconfiguration.

pr_error_pin

1

Input

Connect this port to the dedicated PR_ERROR pin of the FPGA undergoing partial reconfiguration.

pr_done_pin

1

Input

Connect this port to the dedicated PR_DONE pin of the FPGA undergoing partial reconfiguration.

pr_request_pin

1

Output

Connect this port to the dedicated PR_REQUEST pin of the FPGA undergoing partial reconfiguration.

pr_clk_pin

1

Output

Connect this port to the dedicated DCLK of the FPGA undergoing partial reconfiguration.

pr_data_pin[31..0]

16|32

Output

Connect this port to the dedicated DATA[31..0] pins of the FPGA undergoing partial reconfiguration.

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