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Ixiasoft
Visible to Intel only — GUID: fzx1468480633479
Ixiasoft
1.7.1. Partial Reconfiguration Design Guidelines
The following table lists important design guidelines at various steps in the PR design flow:
PR Design Step | Guideline | Reason |
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Designing for partial reconfiguration |
Do not assume initial states in registers inside PR region. After PR is complete, reset all the control path registers to a known state. Unless required for your scenario, you can omit the data path registers from the reset. |
Registers inside the PR region contain undefined values after reconfiguration. Omitting data path registers reduces congestion on reset signals. However, resetting the data registers is required in some cases.3 |
You cannot define synchronous reset as a global signal for Arria® 10 or Cyclone® 10 GX partial reconfiguration. |
PR regions do not support synchronous reset of registers as a global signal, because the Arria® 10 and Cyclone® 10 GX LAB does not support synchronous clear (sclr) signal on a global buffer. The LAB supports the asynchronous clear (aclr) signal driven from a local input, or from a global network row clock. As a result, only the aclr can be a global signal, feeding registers in a PR region. |
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The PRESERVE_FANOUT_FREE_NODE assignment cannot preserve a fanout-free register that has no fanout inside the Verilog HDL or VHDL module in which you define it. To preserve these fanout-free registers, implement the noprune pragma in the source file: (*noprune*)reg r; If there are multiple instances of this module, with only some instances requiring preservation of the fanout-free register, set a dummy pragma on the register in the HDL and also set the PRESERVE_FANOUT_FREE_NODE assignment. This dummy pragma allows the register synthesis to implement the assignment. For example, set the following dummy pragma for a register r in Verilog HDL: (*dummy*)reg r; Then set this instance assignment: set_instance_assignment -name \ PRESERVE_FANOUT_FREE_NODE ON \ -to r; |
The PRESERVE_FANOUT_FREE_NODE assignment does not apply when a register is not used in the Verilog HDL or VHDL module in which it is defined. | |
Partitioning the design |
Register all the inputs and outputs for your PR region. |
Improves timing closure and time budgeting. |
Reduce the number of signals interfacing the PR region with the static region in your design. |
Reduces the wire LUT count. |
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Create a wrapper for your PR region. |
The wrapper creates a common footprint to the static region. |
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Drive all the PR region output ports to inactive state when the PR region is held in reset and the freeze bit is asserted for the PR region. |
Prevents the static region logic from receiving random data during the partial reconfiguration operation. |
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PR boundary I/O interface must be a superset of all the PR persona I/O interfaces. |
Ensures that each PR partition implements the same ports. |
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Preparing for partial reconfiguration |
Complete all pending transactions. |
Ensures that the static region is not in a wait state. |
Maintaining a partially working system during partial reconfiguration |
Hold all outputs to known constant values. |
Ensures that the undefined values the PR region receives during and after the reconfiguration do not affect the PR control logic. |
Initializing after partial reconfiguration |
Initialize after reset. |
Retrieves state from memory or other device resources. |
Debugging the design using Signal Tap Logic Analyzer |
Store all the tapped signals from a persona in one .stp file. | The current version of the Quartus® Prime software supports only one .stp (Signal Tap file) per revision. This limitation requires you to select partitions, one at a time, to tap. |
Do not tap across regions in the same .stp file. |
Ensures consistent interface (boundary) across all personas. |
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Tap only the pre-synthesis signals. In the Node Finder, filter for Signal Tap: pre-synthesis. |
Ensures that the signal tapping of PR personas start from synthesis. |
For example, there are occurrences where registers are being duplicated while simultaneously the register value is undefined after PR. The duplicated registers can result in a mismatch between the parity bit and the data written to the MLAB after PR. Hence, a different value is used to compute the parity bit compared with the actual data written to the MLAB, requiring reset of the data register, or re-write of the value to the register after PR.