Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

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ID 683819
Date 12/12/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. System Debugging Tools Overview 3. Design Debugging with the Signal Tap Logic Analyzer 4. Quick Design Verification with Signal Probe 5. In-System Debugging Using External Logic Analyzers 6. In-System Modification of Memory and Constants 7. Design Debugging Using In-System Sources and Probes 8. Analyzing and Debugging Designs with System Console 9. Intel® Quartus® Prime Pro Edition User Guide Debug Tools Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. System Debugging Tools Overview x
2.1. System Debugging Tools Portfolio 2.2. Tools for Monitoring RTL Nodes 2.3. Stimulus-Capable Tools 2.4. Virtual JTAG Interface Intel® FPGA IP 2.5. System-Level Debug Fabric 2.6. SLD JTAG Bridge 2.7. Partial Reconfiguration Design Debugging 2.8. Preserving Signals for Debugging 2.9. System Debugging Tools Overview Revision History
2.1. System Debugging Tools Portfolio x
2.1.1. System Debugging Tools Comparison 2.1.2. Suggested Tools for Common Debugging Requirements 2.1.3. Debugging Ecosystem
2.2. Tools for Monitoring RTL Nodes x
2.2.1. Resource Usage 2.2.2. Pin Usage 2.2.3. Usability Enhancements
2.2.1. Resource Usage x
2.2.1.1. Overhead Logic
2.2.1.1. Overhead Logic x
2.2.1.1.1. For Signal Tap Logic Analyzer 2.2.1.1.2. For Signal Probe 2.2.1.1.3. For Logic Analyzer Interface
2.2.2. Pin Usage x
2.2.2.1. For Signal Tap Logic Analyzer 2.2.2.2. For Signal Probe 2.2.2.3. For Logic Analyzer Interface
2.2.3. Usability Enhancements x
2.2.3.1. Incremental Routing 2.2.3.2. Automation Via Scripting
2.3. Stimulus-Capable Tools x
2.3.1. In-System Sources and Probes 2.3.2. In-System Memory Content Editor 2.3.3. System Console
2.3.1. In-System Sources and Probes x
2.3.1.1. Push Button Functionality
2.3.2. In-System Memory Content Editor x
2.3.2.1. Generate Test Vectors
2.3.3. System Console x
2.3.3.1. Test Signal Integrity 2.3.3.2. Board Bring-Up and Verification 2.3.3.3. Debug with Available Toolkits
2.6. SLD JTAG Bridge x
2.6.1. SLD JTAG Bridge Index 2.6.2. Instantiating the SLD JTAG Bridge Agent 2.6.3. Instantiating the SLD JTAG Bridge Host
2.7. Partial Reconfiguration Design Debugging x
2.7.1. Debug Fabric for Partial Reconfiguration Designs
2.7.1. Debug Fabric for Partial Reconfiguration Designs x
2.7.1.1. Generation of PR Debug Infrastructure
2.8. Preserving Signals for Debugging x
2.8.1. Preserve for Debug Overview 2.8.2. Marking Signals for Debug
2.8.2. Marking Signals for Debug x
2.8.2.1. Step 1: Enabling Preserve for Debug 2.8.2.2. Step 2: Implement Preserve for Debug Assignments 2.8.2.3. Step 3: Locate and Report Preserve for Debug Nodes
2.8.2.1. Step 1: Enabling Preserve for Debug x
2.8.2.1.1. Enabling Preserve for Debug In Project Settings 2.8.2.1.2. Enabling Preserve for Debug at Instance Level
2.8.2.2. Step 2: Implement Preserve for Debug Assignments x
2.8.2.2.1. HDL Implementation 2.8.2.2.2. Intel® Quartus® Prime Settings Implementation
2.8.2.3. Step 3: Locate and Report Preserve for Debug Nodes x
2.8.2.3.1. Locating Preserve for Debug Nodes 2.8.2.3.2. Reporting Preserve for Debug Nodes
3. Design Debugging with the Signal Tap Logic Analyzer x
3.1. Signal Tap Logic Analyzer Introduction 3.2. Signal Tap Debugging Flow 3.3. Step 1: Add the Signal Tap Logic Analyzer to the Project 3.4. Step 2: Configure the Signal Tap Logic Analyzer 3.5. Step 3: Compile the Design and Signal Tap Instances 3.6. Step 4: Program the Target Hardware 3.7. Step 5: Run the Signal Tap Logic Analyzer 3.8. Step 6: Analyze Signal Tap Captured Data 3.9. Other Signal Tap Debugging Flows 3.10. Signal Tap Logic Analyzer Design Examples 3.11. Custom State-Based Triggering Flow Examples 3.12. Signal Tap File Templates 3.13. Running the Stand-Alone Version of Signal Tap 3.14. Signal Tap Scripting Support 3.15. Signal Tap File Version Compatibility 3.16. Design Debugging with the Signal Tap Logic Analyzer Revision History
3.1. Signal Tap Logic Analyzer Introduction x
Signal Tap Logic Analyzer Instance Signal Tap Logic Analyzer GUI Signal Tap Logic Analyzer and Simulator Integration Signal Tap Logic Analyzer Capabilities 3.1.1. Signal Tap Hardware and Software Requirements
3.3. Step 1: Add the Signal Tap Logic Analyzer to the Project x
3.3.1. Creating a Signal Tap Instance with the Signal Tap GUI 3.3.2. Creating a Signal Tap Instance by HDL Instantiation
3.3.1. Creating a Signal Tap Instance with the Signal Tap GUI x
3.3.1.1. Managing Signal Tap Instances
3.3.2. Creating a Signal Tap Instance by HDL Instantiation x
3.3.2.1. Signal Tap Intel® FPGA IP Parameters
3.4. Step 2: Configure the Signal Tap Logic Analyzer x
3.4.1. Preserving Signals for Monitoring and Debugging 3.4.2. Preventing Changes that Require Full Recompilation 3.4.3. Specifying the Clock, Sample Depth, and RAM Type 3.4.4. Specifying the Buffer Acquisition Mode 3.4.5. Adding Signals to the Signal Tap Logic Analyzer 3.4.6. Defining Trigger Conditions 3.4.7. Specifying Pipeline Settings 3.4.8. Filtering Relevant Samples
3.4.4. Specifying the Buffer Acquisition Mode x
3.4.4.1. Non-Segmented Buffer 3.4.4.2. Segmented Buffer
3.4.5. Adding Signals to the Signal Tap Logic Analyzer x
3.4.5.1. Adding Pre-Synthesis or Post-Fit Nodes 3.4.5.2. Adding Simulator-Aware Signal Tap Nodes 3.4.5.3. Adding Nios® II Processor Signals with a Plug-In 3.4.5.4. Signals Unavailable for Signal Tap Debugging 3.4.5.5. Organizing Signals in the Signal Tap Logic Analyzer
3.4.5.2. Adding Simulator-Aware Signal Tap Nodes x
3.4.5.2.1. Add Simulator-Aware Node Finder Settings
3.4.6. Defining Trigger Conditions x
3.4.6.1. Basic Trigger Conditions 3.4.6.2. Nested Trigger Conditions 3.4.6.3. Comparison Trigger Conditions 3.4.6.4. Advanced Trigger Conditions 3.4.6.5. Custom Trigger HDL Object 3.4.6.6. Specify Trigger Position 3.4.6.7. Power-Up Triggers 3.4.6.8. External Triggers 3.4.6.9. Trigger Condition Flow Control 3.4.6.10. Sequential Triggering 3.4.6.11. State-Based Triggering 3.4.6.12. Trigger Lock Mode
3.4.6.3. Comparison Trigger Conditions x
3.4.6.3.1. Specifying the Comparison Trigger Conditions
3.4.6.4. Advanced Trigger Conditions x
3.4.6.4.1. Examples of Advanced Triggering Expressions
3.4.6.5. Custom Trigger HDL Object x
3.4.6.5.1. Using the Custom Trigger HDL Object 3.4.6.5.2. Required Inputs and Outputs of Custom Trigger HDL Module 3.4.6.5.3. Custom Trigger HDL Module Properties
3.4.6.6. Specify Trigger Position x
3.4.6.6.1. Post-fill Count
3.4.6.7. Power-Up Triggers x
3.4.6.7.1. Enabling a Power-Up Trigger 3.4.6.7.2. Configuring Power-Up Trigger Conditions 3.4.6.7.3. Managing Signal Tap Instances with Run-Time and Power-Up Trigger Conditions
3.4.6.10. Sequential Triggering x
3.4.6.10.1. Configuring the Sequential Triggering Flow
3.4.6.11. State-Based Triggering x
3.4.6.11.1. State-Based Triggering Flow Tab 3.4.6.11.2. State Machine Pane 3.4.6.11.3. Resources Pane 3.4.6.11.4. State Diagram Pane 3.4.6.11.5. Signal Tap Trigger Flow Description Language 3.4.6.11.6. State-Based Storage Qualifier Feature
3.4.6.11.5. Signal Tap Trigger Flow Description Language x
3.4.6.11.5.1. <state_label> 3.4.6.11.5.2. <boolean_expression> 3.4.6.11.5.3. <action_list> 3.4.6.11.5.4. Trigger that Skips Clock Cycles after Hitting Condition 3.4.6.11.5.5. Storage Qualification with Post-Fill Count Value Less than m 3.4.6.11.5.6. Resource Manipulation Action 3.4.6.11.5.7. Buffer Control Actions 3.4.6.11.5.8. State Transition Action
3.4.6.11.6. State-Based Storage Qualifier Feature x
3.4.6.11.6.1. Storage Qualification Feature for the State-Based Trigger Flow
3.4.8. Filtering Relevant Samples x
3.4.8.1. Input Port Mode 3.4.8.2. Transitional Mode 3.4.8.3. Conditional Mode 3.4.8.4. Start/Stop Mode 3.4.8.5. State-Based Mode 3.4.8.6. Showing Data Discontinuities 3.4.8.7. Disable the Storage Qualifier
3.5. Step 3: Compile the Design and Signal Tap Instances x
3.5.1. Recompiling Only Signal Tap Changes 3.5.2. Timing Preservation 3.5.3. Performance and Resource Considerations
3.5.3. Performance and Resource Considerations x
3.5.3.1. Increasing Signal Tap Logic Performance 3.5.3.2. Reducing Signal Tap Device Resources
3.6. Step 4: Program the Target Hardware x
3.6.1. Ensure Compatibility Between .stp and .sof Files
3.7. Step 5: Run the Signal Tap Logic Analyzer x
3.7.1. Changing the Post-Fit Signal Tap Target Nodes 3.7.2. Runtime Reconfigurable Options 3.7.3. Signal Tap Status Messages
3.8. Step 6: Analyze Signal Tap Captured Data x
3.8.1. Viewing Capture Data Using Segmented Buffers 3.8.2. Viewing Data with Different Acquisition Modes 3.8.3. Creating Mnemonics for Bit Patterns 3.8.4. Locating a Node in the Design 3.8.5. Saving Captured Signal Tap Data 3.8.6. Exporting Captured Signal Tap Data 3.8.7. Creating a Signal Tap List File
3.8.2. Viewing Data with Different Acquisition Modes x
3.8.2.1. Continuous Mode and a Storage Qualifier Examples
3.8.3. Creating Mnemonics for Bit Patterns x
3.8.3.1. Adding Mnemonics with a Plug-In
3.9. Other Signal Tap Debugging Flows x
3.9.1. Signal Tap and Simulator Integration 3.9.2. Managing Multiple Signal Tap Configurations 3.9.3. Debugging Partial Reconfiguration Designs with Signal Tap 3.9.4. Debugging Block-Based Designs with Signal Tap 3.9.5. Debugging Devices that use Configuration Bitstream Security 3.9.6. Signal Tap Data Capture with the MATLAB* MEX Function
3.9.1. Signal Tap and Simulator Integration x
3.9.1.1. Generating a Simulation Testbench from Signal Tap Data 3.9.1.2. Create Simulation Testbench Dialog Box Settings
3.9.2. Managing Multiple Signal Tap Configurations x
3.9.2.1. Data Log Pane 3.9.2.2. SOF Manager
3.9.3. Debugging Partial Reconfiguration Designs with Signal Tap x
3.9.3.1. Signal Tap Guidelines for PR Designs 3.9.3.2. PR Design Setup for Signal Tap Debug 3.9.3.3. Performing Data Acquisition in a PR design
3.9.3.2. PR Design Setup for Signal Tap Debug x
3.9.3.2.1. Preparing the Static Region for Signal Tap Debugging 3.9.3.2.2. Preparing the Base Revision for Signal Tap Debugging 3.9.3.2.3. Preparing PR Personas for Signal Tap Debugging
3.9.4. Debugging Block-Based Designs with Signal Tap x
3.9.4.1. Signal Tap Debugging with a Core Partition 3.9.4.2. Signal Tap Debugging with a Root Partition 3.9.4.3. Compiler Snapshots and Signal Tap Debugging
3.9.4.1. Signal Tap Debugging with a Core Partition x
3.9.4.1.1. Partition Boundary Ports Method 3.9.4.1.2. Debug a Core Partition through Partition Boundary Ports 3.9.4.1.3. Export a Core Partition with Partition Boundary Ports 3.9.4.1.4. Signal Tap HDL Instance Method 3.9.4.1.5. Export a Core Partition with Signal Tap HDL Instances 3.9.4.1.6. Debug a Core Partition Exported with Signal Tap HDL Instances
3.9.4.1.4. Signal Tap HDL Instance Method x
3.9.4.1.4.1. Debug a Core Partition Exported with Signal Tap HDL Instances
3.9.4.2. Signal Tap Debugging with a Root Partition x
3.9.4.2.1. Export the Root Partition with SLD JTAG Bridge 3.9.4.2.2. Debugging an Exported Root Partition and Core Partition Simultaneously using the SLD JTAG Bridge
3.9.4.3. Compiler Snapshots and Signal Tap Debugging x
3.9.4.3.1. Add Post-Fit Nodes when Reusing a Partition Containing a Synthesis Snapshot
3.11. Custom State-Based Triggering Flow Examples x
3.11.1. Trigger Example 1: Custom Trigger Position 3.11.2. Trigger Example 2: Trigger When triggercond1 Occurs Ten Times between triggercond2 and triggercond3
3.14. Signal Tap Scripting Support x
3.14.1. Signal Tap Command-Line Options 3.14.2. Data Capture from the Command Line
4. Quick Design Verification with Signal Probe x
4.1. Signal Probe Debugging Flow 4.2. Quick Design Verification with Signal Probe Revision History
4.1. Signal Probe Debugging Flow x
4.1.1. Step 1: Reserve Signal Probe Pins 4.1.2. Step 2: Assign Nodes to Signal Probe Pins 4.1.3. Step 3: Connect the Signal Probe Pin to an Output Pin 4.1.4. Step 4: Compile the Design 4.1.5. (Optional) Step 5: Modify the Signal Probe Pins Assignments 4.1.6. Step 6: Run Fitter-Only Compilation 4.1.7. Step 7: Check Connection Table in Fitter Report
5. In-System Debugging Using External Logic Analyzers x
5.1. About the Intel® Quartus® Prime Logic Analyzer Interface 5.2. Choosing a Logic Analyzer 5.3. Flow for Using the LAI 5.4. Controlling the Active Bank During Runtime 5.5. LAI Core Parameters 5.6. In-System Debugging Using External Logic Analyzers Revision History
5.2. Choosing a Logic Analyzer x
5.2.1. Required Components
5.3. Flow for Using the LAI x
5.3.1. Defining Parameters for the Logic Analyzer Interface 5.3.2. Mapping the LAI File Pins to Available I/O Pins 5.3.3. Mapping Internal Signals to the LAI Banks 5.3.4. Compiling Your Intel® Quartus® Prime Project 5.3.5. Programming Your Intel-Supported Device Using the LAI
5.4. Controlling the Active Bank During Runtime x
5.4.1. Acquiring Data on Your Logic Analyzer
6. In-System Modification of Memory and Constants x
6.1. IP Cores Supporting In System Memory Content Editor 6.2. Debug Flow with the In-System Memory Content Editor 6.3. Enabling Runtime Modification of Instances in the Design 6.4. Programming the Device with the In-System Memory Content Editor 6.5. Loading Memory Instances to the ISMCE 6.6. Monitoring Locations in Memory 6.7. Editing Memory Contents with the Hex Editor Pane 6.8. Importing and Exporting Memory Files 6.9. Access Two or More Devices 6.10. Scripting Support 6.11. In-System Modification of Memory and Constants Revision History
6.10. Scripting Support x
6.10.1. The insystem_memory_edit Tcl Package
6.10.1. The insystem_memory_edit Tcl Package x
6.10.1.1. Getting Information about the insystem_memory_edit Package
7. Design Debugging Using In-System Sources and Probes x
7.1. Hardware and Software Requirements 7.2. Design Flow Using the In-System Sources and Probes Editor 7.3. Compiling the Design 7.4. Running the In-System Sources and Probes Editor 7.5. Tcl interface for the In-System Sources and Probes Editor 7.6. Design Example: Dynamic PLL Reconfiguration 7.7. Design Debugging Using In-System Sources and Probes Revision History
7.2. Design Flow Using the In-System Sources and Probes Editor x
7.2.1. Instantiating the In-System Sources and Probes IP Core 7.2.2. In-System Sources and Probes IP Core Parameters
7.4. Running the In-System Sources and Probes Editor x
7.4.1. In-System Sources and Probes Editor GUI 7.4.2. Programming Your Device With JTAG Chain Configuration 7.4.3. Instance Manager 7.4.4. In-System Sources and Probes Editor Pane
7.4.4. In-System Sources and Probes Editor Pane x
7.4.4.1. Reading Probe Data 7.4.4.2. Writing Data 7.4.4.3. Organizing Data
8. Analyzing and Debugging Designs with System Console x
8.1. Introduction to System Console 8.2. Starting System Console 8.3. System Console GUI 8.4. Launching a Toolkit in System Console 8.5. Using System Console Services 8.6. On-Board Intel® FPGA Download Cable II Support 8.7. MATLAB* and Simulink* in a System Verification Flow 8.8. System Console Examples and Tutorials 8.9. Running System Console in Command-Line Mode 8.10. Using System Console Commands 8.11. Using Toolkit Tcl Commands 8.12. Analyzing and Debugging Designs with the System Console Revision History
8.1. Introduction to System Console x
8.1.1. IP Cores that Interact with System Console 8.1.2. Services Provided through Debug Agents 8.1.3. System Console Debugging Flow
8.2. Starting System Console x
8.2.1. Customizing System Console Startup
8.3. System Console GUI x
8.3.1. System Console Views 8.3.2. Toolkit Explorer Pane 8.3.3. System Explorer Pane 8.3.4. Customizing, Saving, and Resetting the System Console Layout
8.3.1. System Console Views x
8.3.1.1. Main View 8.3.1.2. Autosweep View 8.3.1.3. Dashboard View 8.3.1.4. Eye Viewer
8.3.1.1. Main View x
8.3.1.1.1. Link Pair View
8.4. Launching a Toolkit in System Console x
8.4.1. Available System Debugging Toolkits 8.4.2. Creating Collections from the Toolkit Explorer 8.4.3. Filtering and Searching Interactive Instances
8.5. Using System Console Services x
8.5.1. Locating Available Services 8.5.2. Opening and Closing Services 8.5.3. Using the SLD Service 8.5.4. Using the In-System Sources and Probes Service 8.5.5. Using the Monitor Service 8.5.6. Using the Device Service 8.5.7. Using the Design Service 8.5.8. Using the Bytestream Service 8.5.9. Using the JTAG Debug Service
8.5.3. Using the SLD Service x
8.5.3.1. SLD Commands
8.5.4. Using the In-System Sources and Probes Service x
8.5.4.1. In-System Sources and Probes Commands
8.5.5. Using the Monitor Service x
8.5.5.1. Monitor Commands
8.5.6. Using the Device Service x
8.5.6.1. Device Commands
8.5.7. Using the Design Service x
8.5.7.1. Design Service Commands
8.5.8. Using the Bytestream Service x
8.5.8.1. Bytestream Commands
8.5.9. Using the JTAG Debug Service x
8.5.9.1. JTAG Debug Commands
8.7. MATLAB* and Simulink* in a System Verification Flow x
8.7.1. Supported MATLAB* API Commands 8.7.2. High Level Flow
8.8. System Console Examples and Tutorials x
8.8.1. Nios® II Processor Example
8.8.1. Nios® II Processor Example x
8.8.1.1. Processor Commands
1. Answers to Top FAQs
2. System Debugging Tools Overview
3. Design Debugging with the Signal Tap Logic Analyzer
4. Quick Design Verification with Signal Probe
5. In-System Debugging Using External Logic Analyzers
6. In-System Modification of Memory and Constants
7. Design Debugging Using In-System Sources and Probes
8. Analyzing and Debugging Designs with System Console
9. Intel® Quartus® Prime Pro Edition User Guide Debug Tools Archives
A. Intel® Quartus® Prime Pro Edition User Guides

3.1. Signal Tap Logic Analyzer Introduction

The Signal Tap logic analyzer, available in the Intel® Quartus® Prime software, captures and displays the real-time signal behavior in an Intel FPGA design. Use the Signal Tap logic analyzer to probe and debug the behavior of internal signals during normal device operation, without requiring extra I/O pins or external lab equipment.

By default, the Signal Tap logic analyzer captures data continuously from the signals you specify while the logic analyzer is running. To capture and store only specific signal data, you specify conditions that trigger the start or stop of data capture. A trigger activates when the trigger conditions are met, stopping analysis and displaying the data. You can save the captured data in device memory for later analysis, and filter data that is not relevant.

Signal Tap Logic Analyzer Instance

You enable the logic analyzer functionality by defining one or more instances of the Signal Tap logic analyzer in your project. You can define the properties of the Signal Tap instance in the Signal Tap logic analyzer GUI, or by HDL instantiation of the Signal Tap Logic Analyzer Intel® FPGA IP. After design compilation, you configure the target device with your design (including any Signal Tap instances), which enables data capture and communication with the Signal Tap logic analyzer GUI over a JTAG connection.

Figure 19.  Signal Tap Logic Analyzer Block Diagram

Signal Tap Logic Analyzer GUI

The Signal Tap logic analyzer GUI helps you to rapidly define and modify Signal Tap signal configuration and JTAG connection settings, displays the captured signals during analysis, starts and stops analysis, and displays and records signal data. When you configure a Signal Tap instance in the GUI, Signal Tap preserves the instance settings in a Signal Tap Logic Analyzer file (.stp) for reuse.

Figure 20.  Signal Tap Logic Analyzer GUI

Signal Tap Logic Analyzer and Simulator Integration

You can integrate the Signal Tap logic analyzer with your supported simulator environment. Signal Tap can readily generate a list of "simulator-aware" nodes to tap for any design hierarchy. Tapping this set of nodes then provides full visibility into the entire design hierarchy for direct observation of all internal signal states in your RTL simulator.

Signal Tap also supports automatic RTL simulation testbench creation, allowing you to export acquired Signal Tap hardware data directly into your RTL simulator and observe signals beyond those that you specify for tapping in Signal Tap. You can produce simulation events using the live data traffic to replicate in your simulator.

Signal Tap Logic Analyzer Capabilities

The Signal Tap logic analyzer supports a high number of channels, a large sample depth, fast clock speeds, and other features described in the Key Signal Tap Logic Analyzer Capabilities table.

Table 7.  Key Signal Tap Logic Analyzer Capabilities
Capability Benefit
Multiple logic analyzers in a single device, or in multiple devices in a single chain Capture data from multiple clock domains and from multiple devices at the same time.
Up to 10 trigger conditions for each analyzer instance Send complex data capture commands to the logic analyzer for greater accuracy and problem isolation.
Power-up trigger Capture signal data for triggers that occur after device programming, but before manually starting the logic analyzer.
Custom trigger HDL object Define a custom trigger in Verilog HDL or VHDL and tap specific instances of modules across the design hierarchy, without manual routing of all the necessary connections.
State-based triggering flow Organize triggering conditions to precisely define data capture.
Flexible buffer acquisition modes Precise control of data written into the acquisition buffer. Discard data samples that are not relevant to the debugging of your design.
MATLAB* integration with MEX function Collect Signal Tap capture data into a MATLAB* integer matrix.
RTL simulator integration Easily create a set of nodes to tap for the design hierarchy, and observe all internal signal states in your RTL simulator. Automatic testbench creation allows you to inject acquired Signal Tap data directly into your RTL simulator.
Up to 4,096 channels per logic analyzer instance Samples many signals and wide bus structures.
Up to 128K samples per instance Captures a large sample set for each channel.
Fast clock frequencies Synchronous sampling of data nodes using the same clock tree driving the logic under test.
Compatible with other debugging utilities Use the Signal Tap logic analyzer in tandem with any JTAG-based on-chip debugging tool, such as an In-System Memory Content editor, to change signal values in real-time.
Floating-Point Display Format
  • Single-precision floating-point format IEEE754 Single (32-bit).
  • Double-precision floating-point format IEEE754 Double (64-bit).

Section Content
Signal Tap Hardware and Software Requirements

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