SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide

Download PDF
ID 683815
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. SDI II Intel FPGA IP Design Example Quick Start Guide 2. SDI II Intel FPGA IP Design Example Detailed Description 3. SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench
1. SDI II Intel FPGA IP Design Example Quick Start Guide
2. SDI II Intel FPGA IP Design Example Detailed Description
3. SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

2.1. Parallel Loopback Design Examples

The parallel loopback design examples demonstrate simplex and duplex channel modes with and without external VCXO.
Note: For parallel loopback duplex designs, do not share the TX PLL reference clock with the RX transceiver reference clock. The design logic tunes the TX PLL clock to match the RX recovered clock frequency.
Figure 9. Parallel Loopback with Simplex Mode Block Diagram
Figure 10. Parallel Loopback with Simplex Mode Clocking Scheme
Figure 11. Parallel Loopback with Duplex Mode Block Diagram
Figure 12. Parallel Loopback with Duplex Mode Clocking Scheme
Level Two Title