SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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ID 683815
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel FPGA IP Design Example Quick Start Guide 2. SDI II Intel FPGA IP Design Example Detailed Description 3. SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench
1. SDI II Intel FPGA IP Design Example Quick Start Guide
2. SDI II Intel FPGA IP Design Example Detailed Description
3. SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.5. Compiling and Testing the Design

To compile and run a demonstration test on the hardware design example, follow these steps:
  1. Ensure that the hardware design example generation is complete.
  2. Open quartus/sdi_ii_c10_demo.qpf.
  3. Click Processing > Start Compilation.
  4. Open the Clock Controller parameter editor, and set the clock frequency.
    SDI II Design Examples Si570 (Y2) Tab Si5332 (U64) Tab
    HD/3G-SDI single rate and triple rate Parallel loopback without external VCXO designs Set Target Frequency to 148.5 MHz. Set OUT1 frequency to 100 MHz.
    Serial loopback designs Set Target Frequency to 148.3516 MHz if Dynamic Tx clock switching is enabled. Set OUT1 frequency to 148.5 MHz
    Multi rate Parallel loopback with external VCXO designs Set Target Frequency to 297 MHz. Set OUT1 frequency to 148.5 MHz; if you set the Rx core clock (rx_coreclk) frequency parameter in the IP tab to 148.5/148.35 MHz.
    Serial loopback designs Set Target Frequency to 296.7033 MHz if Dynamic Tx clock switching is enabled. Set OUT1 frequency to 148.5 MHz; if you set the Rx core clock (rx_coreclk) frequency parameter in the IP tab to 148.5/148.35 MHz.
    Figure 5. Si570 (Y2) Tab in the Clock Controller GUI
    Figure 6. Si5332 (U64) Tab in the Clock Controller GUI
  5. After successful compilation, the Intel® Quartus® Prime Pro Edition software generates a .sof file in your specified directory.
  6. Configure the selected Intel® Cyclone® 10 GX device on the development board using the generated .sof file (Tools > Programmer ).
  7. For serial loopback designs, open the System Console to control the internal video pattern generator. Click Tools > System Debugging Tools > System Console.
    Note: Close the Clock Controller GUI and the Programmer window before you open the System Console.
  8. After the initialization, type source ../hwtest/tpg_ctrl.tcl in the System Console to open the pattern generator control user interface. Select your desired video format.

Section Content
Connection and Settings Guidelines
Design Considerations

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