SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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ID 683815
Date 10/08/2021
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel FPGA IP Design Example Quick Start Guide 2. SDI II Intel FPGA IP Design Example Detailed Description 3. SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench
1. SDI II Intel FPGA IP Design Example Quick Start Guide
2. SDI II Intel FPGA IP Design Example Detailed Description
3. SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

2.3. Design Components

The SDI II Intel FPGA IP core design examples require the following components.
Table 9.  Device Under Test (DUT) Components
Design Component Description
SDI II Intel FPGA IP
  • TX
    • The TX core receives the video data from the top level and encodes the necessary information, (e.g. line number (LN), cyclical redundancy check (CRC), payload ID), into the data stream(s).
    • In a multi-rate design, the TX core oversamples the received data up to 11.88 Gbps data rate for every video standard.
    • Specify the assignment of the parallel data interface (tx_parallel_data) to the transceiver based on the 11.88 Gbps data rate settings.
  • RX
    • The RX core receives the parallel data from the Transceiver Native PHY Intel® Arria® 10/Cyclone 10 FPGA IP core and decodes information. This information includes descrambling, realigning data, and extracting the necessary information for user.
    • For a multi-rate design, due to the difference in data widths recovered for different video standards, rearrange rx_parallel_data from the transceiver before passing the data back to the protocol block.

Transceiver Native PHY Intel® Arria® 10/Cyclone 10 FPGA IP

  • TX
    Native PHY IP block that receives parallel data from the SDI II Intel FPGA IP core and serializes the data before transmission.
    • For HD/3G-SDI single-rate and triple-rate designs, enable the simplified data interface option to connect parallel data directly to the tx_dataout signal of the SDI II Intel FPGA IP core.
    • For a multi-rate design, disable this option due to the limitation in the 12G-SDI transceiver PHY settings.
  • RX
    Native PHY block that receives serial data from an external video source.
    • For HD/3G-SDI single-rate and triple-rate designs, enable the simplified data interface option to connect parallel data directly to the rx_datain signal of SDI II Intel FPGA IP core.
    • For a multi-rate design, disable this option due to the limitation in the 12G-SDI transceiver PHY settings.
Note: You must connect the rx_analogreset_ack output signal from this block to the RX Reconfiguration Management module to indicate that the transceiver is in reset.

For the duplex mode transceiver (SDI triple-rate parallel loopback with external VCXO design example), generate a dummy RX only PHY ( sdi_rx_phy.ip) to get the transceiver configuration files (*_CFG0.sv, *_CFG1.sv, …) for RX reconfiguration. The generated configuration files from the duplex mode transceiver may contain some TX registers. You need not reconfigure the registers because only the SDI RX core requires transceiver reconfiguration.

Transceiver PHY Reset Controller Intel FPGA IP

  • TX
    • The reset input of this controller is triggered from the top level.
    • The controller generates the corresponding analog and digital reset signal to the Transceiver Native PHY Intel® Arria® 10/Cyclone 10 FPGA IP block, according to the reset sequencing inside the block.
    • Use the tx_ready output signal from the block as a reset signal to the TX core to indicate that the transceiver is up and running, and ready to receive data from the core.
  • RX
    • The reset input of this controller is triggered by the SDI II Intel FPGA IP core.
    • The controller generates the corresponding analog and digital reset signal to the Transceiver Native PHY Intel® Arria® 10/Cyclone 10 FPGA IP block according to the reset sequencing inside the block.
RX Reconfiguration Management

RX transceiver reconfiguration management block that reconfigures the Transceiver Native PHY Intel® Arria® 10/Cyclone 10 FPGA IP block to receive different data rates from SD-SDI to 12G-SDI standards.

To indicate the status of the transceiver, connect rx_cal_busy and from the transceiver to this block.

Note: If you want to use the reconfiguration management block in your own design, you need to make some assignments in the QSF file. For guidelines about how to make the QSF assignments, refer to the Using Generated Reconfiguration Management for Triple and Multi Rates section in the SDI II Intel FPGA IP User Guide.
TX Reconfiguration Management

TX PLL or transceiver reconfiguration management block that reconfigures the TX PLL or Transceiver Native PHY Intel® Arria® 10/Cyclone 10 FPGA IP block to change the TX clock dynamically for switching between integer and fractional frame rates.

The block requires tx_cal_busy, pll_cal_busy, and from the transceiver, and the PLLs to indicate the status of the transceiver in a TX PLL switching design.

TX PLL/TX PLL Alt
Transmitter PLL block that provides the serial fast clock to Transceiver Native PHY.
  • For TX PLL switching design, TX PLL is always configured to generate integer frame rate while TX PLL Alt is configured to generate fractional frame rate.
  • For TX PLL reference clock switching design, TX PLL is configured to have reference clock 0 to generate integer frame rate and reference clock 1 to generate fractional frame rate.
  • For single-rate and triple-rate designs, this PLL can be either CMU PLL or fPLL.

Move the TX PLL out from the TX top if you want to merge the PLL between multiple channels.

Table 10.  Loopback Components
Component Description
Loopback FIFO
This block contains a dual-clock FIFO (DCFIFO) buffer to handle the data transmission across asynchronous clock domains—the receiver recovered clock and transmitter clock out.
  • The receiver sends the decoded RX data to the transmitter through this FIFO buffer.
  • When the receiver locks, the RX data is written to the FIFO buffer.
  • The transmitter starts reading, encoding, and transmitting the data when half of the FIFO buffer is filled.
Reclock

The parallel loopback without external VCXO design requires this module. This block compares the phase between the receiver and transmitter parallel clocks.

The output interfaces of this block connect to the reconfiguration Avalon Memory-Mapped (Avalon-MM) interfaces of an fPLL or ATX PLL block. If there is any difference in the frequencies between the clock domains, this module generates the necessary signals to reconfigure the fPLL or ATX PLL block to match the clock frequencies as close as possible.

Note: Applicable only for parallel loopback without external VCXO designs.
Table 11.  Video Pattern Generator Components
Component Description
Video Pattern Generator

Basic video pattern generator which supports SD-SDI up to 12G-SDI video formats with 4:2:2 YCbCr. The generator enables you to select static video with colorbar pattern or pathological pattern.

Pattern Gen Control PIO

Provides a memory-mapped interface for controlling the video pattern generator.

JTAG to Avalon Master Bridge

Provides System Console host access to the Parallel I/O (PIO) IP core in the design through the JTAG interface.

Table 12.  Common Block
Component Description
Transceiver Arbiter

This generic functional block prevents transceivers from recalibrating simultaneously when either RX or TX transceivers within the same physical channel require reconfiguration. The simultaneous recalibration impacts applications where RX and TX transceivers within the same channel are assigned to independent IP implementations.

This transceiver arbiter is an extension to the resolution recommended for merging simplex TX and simplex RX into the same physical channel. This transceiver arbiter also assists in merging and arbitrating the Avalon-MM RX and TX reconfiguration requests targeting simplex RX and TX transceivers within a channel as the reconfiguration interface port of the transceivers can only be accessed sequentially. The transceiver arbiter is not required when only either RX or TX transceiver is used in a channel.

The transceiver arbiter identifies the requester of a reconfiguration through its Avalon-MM reconfiguration interfaces and ensures that the corresponding tx_reconfig_cal_busy or rx_reconfig_cal_busy is gated accordingly.

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